RM5261A Просмотр технического описания (PDF) - PMC-Sierra

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RM5261A

Microprocessor with 64-Bit System Bus

PMC-Sierra 

RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet

Preliminary

Revision History

Issue

No. Issue Date

Details of Change

2

September 2001 Added 1.8 V to the feature: 1.65 V or 1.8 V core with 3.3 V or 2.5 V I/O (p9).

Changed recommended operating conditions VccInt to 1.57 V to 1.85 V and

VccP to 1.57 V to 1.85 V. Added VssP commercial and industrial values.

Modified Note 4.

Added reference to VccInt to Power Consumption table. Changed standby

modes to 350. Changed maximum worst case instruction mix to 1250. Modified

Note 1.

Modified SysClock Frequency and SysClock Period values in the Clock

Parameters table.

1

March 2001

Applied PMC-Sierra template to existing MPD (QED) FrameMaker document.

Revised features list, Absolute Maximum Ratings table, Recommended

Operating Conditions table, DC Electrical Characteristics table, Power

Consumption table, Clock Parameters table and the System Interface

Parameters table.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

3

Document ID: PMC-2002240, Issue 2

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