MSC23V26468TD-60BS8 Просмотр технического описания (PDF) - Oki Electric Industry

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MSC23V26468TD-60BS8

2,097,152-Word x 64-Bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO

Oki Electric Industry 

Semiconductor

MSC23V26468TD

Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles

(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.

2. The AC characteristics assume tT = 2ns.

3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are

measured between VIH and VIL.

4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100pF.

The output timing reference levels are VOH = 2.0V and VOL = 0.8V.

5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met.

tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then

the access time is controlled by tCAC.

6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met.

tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then

the access time is controlled by tAA.

7. tCEZ(Max.), tREZ(Max.), tWEZ(Max.) and tOEZ(Max.) define the time at which the output achieves the open

circuit condition and are not referenced to output voltage levels.

8. tCEZ or tREZ must be satisfied for open circuit condition.

9. tRCH or tRRH must be satisfied for a read cycle.

10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only. If tWCS ≥ tWCS(Min.), then the cycle is an early write cycle and the

data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD(Min.), tRWD

≥ tRWD(Min.), tAWD ≥ tAWD(Min.) and tCPWD ≥ tCPWD(Min.), then the cycle is a read modify write cycle and

data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied,

then the condition of the data out (at access time) is indeterminate.

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