PM5356-BI Просмотр технического описания (PDF) - PMC-Sierra
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PM5356-BI Datasheet PDF : 307 Pages
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RELEASED
S/UNI-622-MAX
DATASHEET
PMC-1980589
ISSUE 6
PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
SATURN USER NETWORK INTERFACE (622-MAX)
10.7 TRANSMIT LINE INTERFACE (CSPI-622) .................................................................... 56
10.8 TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP)........................................... 57
10.9 TRANSMIT LINE OVERHEAD PROCESSOR (TLOP)................................................... 58
10.10 TRANSMIT PATH OVERHEAD PROCESSOR (TPOP) ................................................. 58
10.11 TRANSMIT ATM CELL PROCESSOR (TXCP)............................................................... 60
10.12 ATM UTOPIA SYSTEM INTERFACES ........................................................................... 61
10.13 JTAG TEST ACCESS PORT .......................................................................................... 63
10.14 MICROPROCESSOR INTERFACE................................................................................ 63
11
NORMAL MODE REGISTER DESCRIPTION .............................................................................. 69
12
TEST FEATURES DESCRIPTION.............................................................................................. 227
12.1 MASTER TEST AND TEST CONFIGURATION REGISTERS ...................................... 227
12.2 JTAG TEST PORT........................................................................................................ 230
13
OPERATION ............................................................................................................................... 237
13.1 SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE .......................... 237
13.2 ATM CELL DATA STRUCTURE.................................................................................... 242
13.3 SETTING SONET OR SDH MODE OF OPERATION................................................... 243
13.4 BIT ERROR RATE MONITOR ...................................................................................... 245
13.5 AUTO ALARM CONTROL CONFIGURATION.............................................................. 246
13.6 CLOCKING OPTIONS.................................................................................................. 247
13.7 LOOPBACK OPERATION ............................................................................................ 248
13.8 1+1 APS SUPPORT ..................................................................................................... 252
13.9 JTAG SUPPORT .......................................................................................................... 253
13.10 BOARD DESIGN RECOMMENDATIONS .................................................................... 258
13.11 POWER SUPPLIES ..................................................................................................... 259
13.12 INTERFACING TO ECL OR PECL DEVICES............................................................... 262
13.13 CLOCK SYNTHESIS AND RECOVERY....................................................................... 264
13.14 SYSTEM INTERFACE DLL OPERATION..................................................................... 265
14
FUNCTIONAL TIMING................................................................................................................ 267
14.1 PARALLEL LINE INTERFACE...................................................................................... 267
14.2 ATM UTOPIA LEVEL 2 SYSTEM INTERFACE............................................................. 268
14.3 ATM UTOPIA LEVEL 3 SYSTEM INTERFACE............................................................. 269
15
ABSOLUTE MAXIMUM RATINGS .............................................................................................. 272
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ii
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