MPC950 Просмотр технического описания (PDF) - Motorola => Freescale
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MPC950 Datasheet PDF : 13 Pages
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‘1’
‘1’
‘1’
‘0’
‘0’
16.66MHz
MPC950
fsela
fselb
fselc
fseld
FBsel
Input Ref
1
Qa
1
Qb
2
Qc
5
Qd
66.66MHz
33.33MHz
33.33MHz
66.66MHz
Figure 1. Dual Frequency Configuration
‘1’
‘1’
‘1’
‘1’
‘0’
16.66MHz
MPC950
fsela
fselb
fselc
fseld
FBsel
Input Ref
1
Qa
1
Qb
2
Qc
5
Qd
66.66MHz
33.33MHz
33.33MHz
33.33MHz
Figure 3. Dual Frequency Configuration
‘1’
‘0’
‘0’
‘0’
75MHz
MPC951
fsela
fselb
fselc
fseld
Ext_FB
Input Ref
1
Qa
1
Qb
2
Qc
5
Qd
1
75MHz
75MHz
75MHz
75MHz
Figure 5. “Zero” Delay Buffer
MPC950 MPC951
‘1’
‘0’
‘0’
‘1’
‘1’
33.33MHz
MPC950
fsela
fselb
fselc
fseld
FBsel
Input Ref
1
Qa
1
Qb
2
Qc
5
Qd
66.66MHz
66.66MHz
66.66MHz
33.33MHz
Figure 2. Dual Frequency Configuration
‘0’
‘0’
‘1’
‘1’
‘0’
20MHz
MPC950
fsela
fselb
fselc
fseld
FBsel
Input Ref
1
Qa
1
Qb
2
Qc
5
Qd
160MHz
80MHz
40MHz
40MHz
Figure 4. Triple Frequency Configuration
‘0’
‘0’
‘0’
‘1’
25MHz
MPC951
fsela
fselb
fselc
fseld
Ext_FB
Input Ref
1
Qa
1
Qb
2
Qc
5
Qd
1
100MHz
50MHz
50MHz
25MHz
Figure 6. “Zero” Delay Frequency Multiplier
Jitter Performance of the MPC950/951
With the clock rates of today’s digital systems continuing
to increase more emphasis is being placed on clock
distribution design and management. Among the issues
being addressed is system clock jitter and how that affects
the overall system timing budget. The MPC950/951 was
designed to minimize clock jitter by employing a differential
bipolar PLL as well as incorporating numerous power and
ground pins in the design. The following few paragraphs will
outline the jitter performance of the MPC950/951, illustrate
the measurement limitations and provide guidelines to
minimize the jitter of the device.
The most commonly specified jitter parameter is
cycle–to–cycle jitter. Unfortunately with today’s high
performance measurement equipment there is no way to
measure this parameter for jitter performance in the class
demonstrated by the MPC950/951. As a result different
methods are used which approximate cycle–to–cycle jitter.
The typical method of measuring the jitter is to accumulate a
large number of cycles, create a histogram of the edge
placements and record peak–to–peak as well as standard
deviations of the jitter. Care must be taken that the measured
edge is the edge immediately following the trigger edge. If
this is not the case the measurement inaccuracy will add
significantly to the measured jitter. The oscilloscope cannot
collect adjacent pulses, rather it collects data from a very
large sample of pulses. It is safe to assume that collecting
pulse information in this mode will produce jitter values
somewhat larger than if consecutive cycles were measured,
therefore, this measurement will represent an upper bound of
cycle–to–cycle jitter. Most likely, this is a conservative
estimate of the cycle–to–cycle jitter.
There are two sources of jitter in a PLL based clock driver,
the commonly known random jitter of the PLL and the less
intuitive jitter caused by synchronous, different frequency
outputs switching. For the case where all of the outputs are
TIMING SOLUTIONS
7
BR1333 — Rev 6
MOTOROLA
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