MPC8540(2004) Просмотр технического описания (PDF) - Freescale Semiconductor

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MPC8540
(Rev.:2004)

PowerQUICC III™ Integrated Host Processor Reference Manual

Freescale Semiconductor 

Part I—Overview

Overview

Memory Map

Signal Descriptions

Reset, Clocking, and Initialization

Part II—e500 Core Complex and L2 Cache

e500 Core Complex Overview

e500 Register Summary

L2 Look-Aside Cache/SRAM

Part III—Memory and I/O Interfaces

e500 Coherency Module

DDR Memory Controller

Programmable Interrupt Controller

I2C Interface

DUART

Local Bus Controller

Three-Speed Ethernet Controllers

DMA Controller

PCI/PCI-X Bus Interface

RapidIO Interface

Part IV—Global Functions and Debug

Global Utilities

Performance Monitor

Debug Features and Watchpoint Facility

10/100 Fast Ethernet Controller

Appendix A—Revision History

Glossary of Terms and Abbreviations

Register Index (Memory-Mapped Registers)

General Index

I

1

2

3

4

II

5

6

7

III

8

9

10

11

12

13

14

15

16

17

IV

18

19

20

21

A

GLO

REG

IND

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