PPC5645SF0CLT Просмотр технического описания (PDF) - Freescale Semiconductor

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PPC5645SF0CLT

Qorivva MPC5645S Microcontroller

Freescale Semiconductor 

SoC features

Table 2. Operating mode summary

Clock sources

Wake-up time1

RUN

HALT

STOP

STAN

DBY

POR

On OP OP OP2 On OP OP On OP On OP — — FP — — — — — — —

CG OP OP OP2 On OP OP On OP On OP OP OP FP — — — — — — 30 µs 3

CG CG CG OP2 CG CG CG OP OP On OP OP OP LP 350 µs 4 µs 20 µs 1 ms 200 µs — 30 µs 3

Off Off Off 64K4 Off Off Off OP OP On OP OP OP LP 350 µs 8 µs 100 µs 1 ms 200 µs Var 28 µs

Off Off Off 8K5 Off Off Off OP OP On OP OP OP LP 200 µs 8 µs 100 µs 1 ms 200 µs Var 28 µs

—

— — — — — — — — — — — — — 500 µs 8 µs 100 µs 1 ms 200 µs — BAM6

Table key:

• On — Powered and clocked

• OP — Optionally configurable to be enabled or disabled (clock gated)

• CG — Clock Gated, Powered but clock stopped

• Off — Powered off and clock gated

• FP — VREG Full Performance mode

• LP — VREG Low Power mode, reduced output capability of VREG but lower power consumption

• Var — Variable duration, based on the required reconfiguration and execution clock speed

• BAM — Boot Assist Module Software and Hardware used for device start-up and configuration

1 A high level summary of some key durations that need to be considered when recovering from low power modes. This

does not account for all durations at wake up. Other delays will be necessary to consider including, but not limited to the

external supply start-up time.

IRC Wake-up time must not be added to the overall wake-up time as it starts in parallel with the VREG.

All other wake-up times must be added to determine the total start-up time.

2 Either 64 KB or 8 KB available.

3 Flash configured in disabled mode.

4 64 KB of the RAM contents is retained, but not accessible in STANDBY mode.

5 8 KB of the RAM contents is retained, but not accessible in STANDBY mode.

6 Dependent on boot option after reset.

Additional notes on low power operation:

• Fast wake-up using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM on exit from low

power modes

• The 16 MHz internal RC oscillator supports low speed code execution and clocking of peripherals when it is selected

as the system clock and can also be used as the PLL input clock source to provide fast start-up without the external

oscillator delay

• The device includes an internal voltage regulator that includes the following features:

— Regulates input to generate all internal supplies

— Manages power gating

— External ballast transistor for high power regulator

— Low-Power and Ultra-Low-Power regulators support operation when in STOP and STANDBY modes,

respectively, to minimize power consumption

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

8

Freescale Semiconductor

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