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MPC7455

RISC Microprocessor Hardware Specifications

Freescale Semiconductor 

Electrical and Thermal Characteristics

5.2.3 L3 Clock AC Specifications

The L3_CLK frequency is programmed by the L3 configuration register (L3CR[6:8]) core-to-L3 divisor ratio. See

Table 18 for example core and L3 frequencies at various divisors. Table 10 provides the potential range of L3_CLK

output AC timing specifications as defined in Figure 7.

The maximum L3_CLK frequency is the core frequency divided by two. Given the high core frequencies available

in the MPC7455, however, most SRAM designs will be not be able to operate in this mode using current technology

and, as a result, will select a greater core-to-L3 divisor to provide a longer L3_CLK period for read and write access

to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in Table 10 is considered to be the practical

maximum in a typical system. The maximum L3_CLK frequency for any application of the MPC7455 will be a

function of the AC timings of the MPC7455, the AC timings for the SRAM, bus loading, and printed-circuit board

trace length, and may be greater or less than the value given in Table 10.

Freescale is similarly limited by system constraints and cannot perform tests of the L3 interface on a socketed part

on a functional tester at the maximum frequencies of Table 10. Therefore, functional operation and AC timing

information are tested at core-to-L3 divisors which result in L3 frequencies at 200 MHz or less.

Table 10. L3_CLK Output AC Timing Specifications

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades

Min

Typ

Max

Unit Notes

L3 clock frequency

fL3_CLK

75

250

—

MHz

1

L3 clock cycle time

tL3_CLK

—

4.0

13.3

ns

L3 clock duty cycle

tCHCL/tL3_CLK

50

%

2

L3 clock output-to-output skew (L1_CLK0 to tL3CSKW1

—

—

200

ps

3

L1_CLK1)

L3 clock output-to-output skew (L1_CLK[0:1] tL3CSKW2

—

—

100

ps

4

to L1_ECHO_CLK[2:3])

L3 clock jitter

—

—

±50

ps

5

Notes:

1. The maximum L3 clock frequency will be system dependent. See Section 5.2.3, “L3 Clock AC Specifications,” for

an explanation that this maximum frequency is not functionally tested at speed by Freescale.

2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.

3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control

signals which are common to both SRAM chips in the L3.

4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for

PB2 or late write SRAM. This parameter is critical to the write data signals which are separately latched onto each

SRAM part by these pairs of signals.

5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3

address/data/control signals equally and, therefore, is already comprehended in the AC timing and does not have

to be considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock

period caused by supply voltage noise or thermal effects. This must be accounted for, along with clock skew, in

any L3 timing analysis.

MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

20

Freescale Semiconductor

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