MP111A Просмотр технического описания (PDF) - Cirrus Logic
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MP111A Datasheet PDF : 5 Pages
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MP111
Product Innova tionFrom
GENERAL
Please read Application Note 1 "General Operating Consid-
erations" which covers stability, power supplies, heat sinking,
mounting, current limit, SOA interpretation, and specification
interpretation. Visit www.cirrus.com for design tools that help
automate tasks such as calculations for stability, internal power
dissipation, current limit, heat sink selection, Apex Precision
Power's complete Application Notes library, Technical Seminar
Workbook and Evaluation Kits.
GROUND PINS
The MP111 has two ground pins (pins 3, 32). These pins
provide a return for the internal capacitive bypassing of the
small signal portions of the MP111. The two ground pins are
not connected together on the substrate. Both of these pins
are required to be connected to the system signal ground.
SAFE OPERATING AREA
The MOSFET output stage of the MP111 is not limited by
second breakdown considerations as in bipolar output stages.
Only thermal considerations and current handling capabilities
limit the SOA (see Safe Operating Area graph on previous page).
The output stage is protected against transient flyback by the
parasitic body diodes of the output stage MOSFET structure.
However, for protection against sustained high energy flyback
external fast-recovery diodes must be used.
COMPENSATION
The external compensation capacitor CC is connected
between pins 5 and 6. Unity gain stability can be achieved with
any capacitor value larger than 100pF for a minimum phase
margin of 45 degrees. At higher gains more phase shift can
usually be tolerated in most designs and the compensation
capacitor value can be reduced resulting in higher bandwidth
and slew rate. Use the typical operating curves as a guide to
select CC for the application. An NPO (COG) type capacitor is
required rated for the full supply voltage (100V).
OVERVOLTAGE PROTECTION
Although the MP111 can withstand differential input voltages
up to ±25V, additional external protection is recommended. In
most applications 1N4148 signal diodes connected anti-parallel
across the input pins is sufficient. In more demanding applica-
tions where bias current is important diode connected JFETs
such as 2N4416 will be required. See Q1 and Q2 in Figure 1.
In either case the differential input voltage will be clamped to
±0.7V. This is usually sufficient overdrive to produce the maxi-
mum power bandwidth. Some applications will also need over
voltage protection devices connected to the power supply rails.
Unidirectional zener diode transient suppressors are recom-
mended. The zeners clamp transients to voltages within the
power supply rating and also clamp power supply reversals to
ground. Whether the zeners are used or not the system power
supply should be evaluated for transient performance including
power-on overshoot and power-off polarity reversals as well as
line regulation. See Z1 and Z2 in Figure 1.
POWER SUPPLY BYPASSING
Bypass capacitors to power supply terminals +VS and -VS
must be connected physically close to the pins to prevent
local parasitic oscillation in the output stage of the MP111. Use
electrolytic capacitors at least 10µF per output amp required.
Bypass the electrolytic capacitors with high quality ceramic
capacitors (X7R) 0.1µF or greater. In most applications power
supply terminals +Vb and -Vb will be connected to +VS and
-VS respectively. Supply voltages +Vb and -Vb are bypassed
internally but both ground pins 3 and 32 must be connected to
the system signal ground to be effective. In all cases power to
the buffer amplifier stage of the MP111 at pins 8 and 25 must
be connected to +Vb and
-Vb at pins 4 and 30 respectively. Provide local bypass
capacitors at pins 8 and 25. See the external connections
diagram on page 1.
+Vs Z1
+Vs
-IN
34
+Vb 3
GND
Q2
Q1
33
GND
+IN
-Vb 32
-Vs
OUT
RIN 34
IN
33
RF
27
ILIM-
28
ILIM+
RP
OUT
11-13
20-22
RLIM
RL
Z2
-Vs
FIGURE 1
OVERVOLTAGE PROTECTION
FIGURE 2
4 WIRE CURRENT LIMIT
CURRENT LIMIT
The two current limit sense lines are to be connected directly
across the current limit sense resistor. For the current limit to
work correctly pin 28 must be connected to the amplifier output
side and pin 27 connected to the load side of the current limit
resistor RLIM as shown in Figure 2. This connection will bypass
any parasitic resistances RP, formed by socket and solder joints
as well as internal amplifier losses. The current limiting resistor
may not be placed anywhere in the output circuit except where
shown in Figure 2. The value of the current limit resistor can
be calculated as follows: RLIM = .65/ILIMIT
BOOST OPERATION
With the boost feature the small signal stages of the amplifier
are operated at a higher supply voltages than the amplifier's
high current output stage. +Vb (pins 4,8) and -Vb (pins 25,30)
are connected to the small signal stages and +VS (pins 14-16)
and -VS (pins 17-19) are connected to the high current output
stage. An additional 10V on the +Vb and -Vb pins is sufficient
to allow the small signal stages to drive the output stage into
the triode region and improve the output voltage swing for extra
efficient operation when required. When the boost feature is
not needed +VS and -VS are connected to the +Vb and -Vb
pins respectively. The +Vb and -Vb pins must not be operated
at supply voltages less than +VS and -VS respectively.
BACKPLATE GROUNDING
The substrate of the MP111 is an insulated metal substrate.
It is required that it be connected to signal ground. Connect pin
2 (back plate) to signal ground. The back plate will then be AC
grounded to signal ground through a 1µF capacitor.
4
MP111U
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