MMA8450Q Просмотр технического описания (PDF) - Freescale Semiconductor
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MMA8450Q Datasheet PDF : 57 Pages
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2.3 I2C Interface Characteristic
Table 4. I2C Slave Timing Values(1)
Parameter
SCL Clock Frequency
Pullup = 1 kΩ Cb = 400 pF
Pullup = 1 kΩ Cb = 20 pF
Symbol
I2C Standard Mode
Unit
Min
Max
fSCL
0
400
kHz
0
TBD
kHz
Bus Free Time between STOP and START Condition
Repeated START Hold Time
Repeated START Setup Time
STOP Condition Setup Time
SDA Data Hold Time(2)
SDA Valid Time (5)
SDA Valid Acknowledge Time (6)
SDA Setup Time
SCL Clock Low Time
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tVD;DAT
tVD;ACK
tSU;DAT
tLOW
1.3
0.6
0.6
0.6
50(3)
100(7)
4.7
μs
μs
μs
μs
(4)
μs
0.9(4)
μs
0.9(4)
μs
Ns
μs
SCL Clock High Time
tHIGH
4
μs
SDA and SCL Rise Time
SDA and SCL Fall Time (3) (8) (9) (10)
tr
1000
Ns
tf
300
Ns
Pulse width of spikes on SDA and SCL that must be suppressed by input filter
tSP
50
Ns
1. All values referred to VIH (min) and VIL (max) levels.
2. tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
3. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
4. The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of tVD;DAT or tVD;ACK
by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock
stretches the SCL, the data must be valid by the setup time before it releases the clock.
5. tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
6. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
7. A Fast-mode I2C device can be used in a Standard-mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the
SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C
specification) before the SCL line is released. Also the acknowledge timing must meet this setup time
8. Cb = total capacitance of one bus line in pF.
9. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.
This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding
the maximum specified tf.
10.In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for
this when considering bus timing
MMA8450Q
8
Sensors
Freescale Semiconductor, Inc.
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