MM74HC4046 Просмотр технического описания (PDF) - Fairchild Semiconductor

Номер в каталоге

Компоненты Описание

производитель

MM74HC4046

CMOS Phase Lock Loop

Fairchild Semiconductor 

Detailed Circuit Description (Continued)

FIGURE 2. Logic Diagram for VCO

The input to the VCO is a very high impedance CMOS

input and so it will not load down the loop filter, easing the

filters design. In order to make signals at the VCO input

accessible without degrading the loop performance a

source follower transistor is provided. This transistor can

be used by connecting a resistor to ground and its drain

output will follow the VCO input signal.

An inhibit signal is provided to allow disabling of the VCO

and the source follower. This is useful if the internal VCO is

not being used. A logic high on inhibit disables the VCO

and source follower.

The output of the VCO is a standard high speed CMOS

output with an equivalent LSTTL fanout of 10. The VCO

output is approximately a square wave. This output can

either directly feed the comparator input of the phase com-

parators or feed external prescalers (counters) to enable

frequency synthesis.

PHASE COMPARATORS

All three phase comparators share two inputs, Signal In

and Comparator In. The Signal In has a special DC bias

network that enables AC coupling of input signals. If the

signals are not AC coupled then this input requires logic

levels the same as standard 74HC. The Comparator input

is a standard digital input. Both input structures are shown

in Figure 3.

The outputs of these comparators are essentially standard

74HC voltage outputs. (Comparator II is 3-STATE.)

FIGURE 3. Logic Diagram for Phase Comparator I and the common input circuit for all three comparators

9

www.fairchildsemi.com

Share Link: