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MLX90805

Intelligent Triac Controller

Melexis Microelectronic Systems  

MLX90805

Intelligent Triac Controller

Maximum phase angle

Independent of the phase angle definitions in the

ROM table, a maximum phase angle can be defined.

This is the phase angle that will be applied immedi-

ately after the power on sequence, and is therefore

the first phase angle in the soft start sequence.

This maximum phase angle is defined in MIN[9:0]

with the formula:

MIN[9:0] = Tini * 2 * Fmains - 10

With:

Tini = the initial phase angle (in msec)

Fmains = frequency of the mains (in Hz)

Default value:

Tini = 7 msec and Fmains = 50Hz, thus MIN[9:0] is

690.

Soft start time duration

There are 5 bits ATN[4:0] used to define the duration

of the soft start time. The bits can be calculated with

following formula:

Ts = ((Tini – Tmin) * ATTN ) / 62.5

With:

Ts = the duration of the soft start (in sec.)

Tini = the initial phase angle defined by MIN[9:0] (in

msec)

Tmin = the phase angle corresponding to the value

in the highest ROM address (in msec)

ATTN = bin2dec(ATN[4:0]+1), a value between 2

and 32.

Default value:

Tini = 8msec, Tmin = 1.84 msec, ATTN = 32, thus Ts

= 3.15 sec.

Firing pulse duration

The duration of the firing pulses can be defined by

the bits DUTS[1:0] according to following table.

The default value is 20 usec.

Enable Retriggering

With bit RTRIG set to 1, triac retriggering is enabled.

The retriggering circuit checks whether the triac is

ON, if not additional firing pulses are generated

every 20us (with respect to the end of the previous

firing pulse) until firing of the triac.

With bit RTRIG set to 0, triac retriggering is disabled.

For each triac firing two pulses are generated with a

delay of 20 usec (with respect to the end of the

previous firing pulse).

The default value is triggering enabled.

Retriggering Mask

With the option MINA[3:0] it is possible to define a

zone at the end of each half cycle of the mains

voltage, where it is impossible to generate

retriggering pulses. This has two purposes:

With some (non inductive) loads the current can

become quite small at the end of each half cycle.

This can eventually activate the retriggering circuit

which will unnecessarily generate additional pulses

thus increasing the current consumption.

When generating a retriggering pulse just before the

zero crossing, this pulse could overlap to the next

half period. With some (non inductive) loads this can

lead to false triggering at full power and must be

avoided.

The bits MINA[3:0] are defined according to the

following formula:

Tmina * 2 * Fmains = MINA[3:0] * 64

With:

Tmina = the phase angle from which retriggering is

prohibited (in msec)

Fmains = frequency of the mains (in Hz)

Default value:

MINA[3:0]=1101'b=13'd and Fmain = 50Hz, this

means that retriggering is prohibited at 8.32ms.

DUTS1

0

0

1

1

DUTS0

0

1

0

1

Duration in µS

320

80

40

20

Soft start only Function regulator

See page 8

2-wire or 3-wire potentiometer

connection.

See pages 9 and 10

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RePvaYg.Xe 7

22/Aug/98 Rev 1.2 17P/Magaey7/00

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