ML674001 Просмотр технического описания (PDF) - Oki Electric Industry

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производитель

ML674001

32-bit ARM-Based General-Purpose Microcontroller

Oki Electric Industry 

OKI Semiconductor

FEDL674001-01

ML674001/67Q4002/67Q4003

Pin

LQFP BGA Symbol

79 K13 PIOB[3]

80 J11 PIOB[4]

81 K12 PIOB[5]

82 J13 PIOC[0]

83 J10 PIOC[1]

84 J12 GND

85 H13 XBS_N[0]

86 H12 XBS_N[1]

87 H10 VDD_CORE

88 H11 PIOD[0]

89 G12 PIOD[1]

90 G10 GND

91 G11 VDD_IO

92 G13 PIOD[2]

93 F11 PIOD[3]

94 F10 PIOD[4]

95 F12 PIOD[5]

96 E12 BSEL[0]

97 F13 BSEL[1]

98 E10 PIOE[5]

99 D12 PIOE[6]

100 E13 PIOE[7]

101 E11 PIOE[8]

102 D11 PIOE[9]

103 D13 PIOE[0]

104 C12 PIOE[1]

105 D10 PIOE[2]

106 C13 TDI

107 B12 TDO

108 B13 nTRST

109 A13 NC

110 A12 NC

111 C11 CKO

112 A11 JSEL

113 C10 TMS

114 B11 TCK

115 A10 DRAME_N

Primary Function

I/O

Description

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I/O

I/O

GND

O

O

VDD

I/O

General port (with interrupt function)

General port (with interrupt function)

GND

External bus byte select (LSB)

External bus byte select (MSB)

CORE power supply

General port (with interrupt function)

I/O General port (with interrupt function)

GND

VDD

I/O

GND

I/O power supply

General port (with interrupt function)

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I Select boot device

I Select boot device

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I/O General port (with interrupt function)

I JTAG data Input

O JTAG data out

I JTAG reset

— NC

— NC

O Clock output

I JTAG select

I JTAG mode select

I JTAG clock

I DRAM enable

Secondary Function

Symbol

I/O

Description

DREQCLR[1]

O DREQ Clear Signal

(CH1)

TCOUT[0]

O DMAC Terminal Count

(CH0)

TCOUT[1]

O DMAC Terminal Count

(CH1)

PWMOUT[0]

O PWM output (CH0)

PWMOUT[1]

O PWM output (CH1)

—

—

—

—

—

—

—

—

XWAIT

I Wait input signal for I/O

Banks

XCAS_N

O Column address strobe

(SDRAM)

—

—

—

—

XRAS_N

O Row address strobe

(SDRAM/EDO)

XSDCLK

O Clock for SDRAM

XSDCS_N

O Chip select for SDRAM

XSDCKE

O Clock enable (SDRAM)

—

—

—

—

EXINT[0]

I Interrupt input

EXINT[1]

I Interrupt input

EXINT[2]

I Interrupt input

EXINT[3]

I Interrupt input

EFIQ_N

I FIQ input

SCLK

I/O SSIO clock

SDI

I SSIO Serial Data In

SDO

O SSIO Serial Data Out

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

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