OKI Semiconductor
FEDL674000-02
ML674000
PIN DESCRIPTION
Pin Name I/O
Description
Primary/
Secondary Logic
System
RESET_N
I Reset input
—
Negative
Crystal oscillator connection or external clock input.
OSC0
I Connect a crystal oscillator (16 MHz to 33 MHz), if used, to OSC0 and
—
OSC1_N.
Crystal oscillator connection.
OSC1_N
O Leave this pin unconnected if using external clock input.
—
TBE
I Test pin. Drive at High level.
—
Negative
Debugging support.
DBGRQ
I Debugging pin. Normally connect to ground.
—
Positive
DBGACK
O Debugging pin. Normally leave open.
—
Positive
TCK
I Debugging pin. Normally connect to ground.
—
—
TMS
I Debugging pin. Normally drive at High level.
—
Positive
nTRST
I Debugging pin. Normally connect to ground.
—
Negative
TDI
I Debugging pin. Normally drive at High level.
—
Positive
TDO
O Debugging pin. Normally leave open.
—
Positive
General-purpose I/O ports
PIOA[15:0]
General-purpose port.
I/O Not available for use as port pins when secondary functions are in use.
Primary Positive
PIOB[15:0]
General-purpose port.
Not available for use as port pins when secondary functions are in use. Note
I/O that enabling DRAM controller with MODE[2:0] inputs permanently
configures PIOB[15:9] for their secondary functions, making them
unavailable for use as port pins.
Primary
Positive
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