ML7048 Просмотр технического описания (PDF) - Oki Electric Industry
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ML7048 Datasheet PDF : 20 Pages
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1Semiconductor
PEDL7048-01-01
ML7048-01
DOUT1, DOUT2, DOUT3
When P/S is “0” and 3-channel independent serial interface is selected, DOUT1 is the PCM signal output pin for
Channel 1, DOUT2 is for Channel 2, and DOUT3 is for Channel 3.
When P/S is “1” and 3-channel continuous serial interface is selected, DOUT1 is the PCM signal output pin for
each channel and data is output in the order of Channel 1, Channel 2, and Channel 3. At that time, DOUT2 and
DOUT3 are at a high impedance state.
The PCM signal is sequentially output starting from MSD in synchronization with the rise of BCLK. (MSD may
be output at the rising edge of XSYNC depending on the timing of BCLK and XSYNC.) These pins are at a high
impedance during the time other than PCM data output bits.
These pins also are at a high impedance during power down mode and power saving mode.
These pins must be internally connected to pull-up resistors because the output form is of open-drain. For coding
law, the ITU-T Recommend µ-law is employed.
Input/output level
+ full scale
+0
–0
– full scale
PCMIN / PCMOUT
µ-law
MDDDDDDD
S2345678
D
10000000
11111111
01111111
00000000
Table 1 Coding law
VDDA
+5V power supply for analog signal circuits.
Use an analog power supply system of equipment used.
Connect a bypass capacitor of 1 µF with excellent high frequency characteristics and a capacitor of 10 µF between
this pin and the AG pin.
AG
Ground pin for analog signal circuits.
VDD
+5V power supply pin for digital signal circuits.
Although this pin and VDDA are not connected internally, these pins must be connected on the printed circuit
board.
DG
Ground pin for digital signal circuits.
Although this pin and AG are not connected internally, these pins must be connected on the printed circuit board.
TEST2, TEST3
These pins are used for device test.
These device test pins must be connected to the DG pin.
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