ML7033 Просмотр технического описания (PDF) - Oki Electric Industry
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ML7033 Datasheet PDF : 51 Pages
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1Semiconductor
FEDL7033-02
ML7033
Pin
Symbol
Type
Description
38
VDDD
— Power Supply for Internal Digital Circuit
39
MCK
I
Master Clock (2.048/4.096 MHz)
40
BCLK
I
PCM Data Shift Clock
41
DG
— Digital Ground
42
PCMIN
I
PCM Data Input
43
PCMOSY
O
PCM Data Output Indicator for Time-Slot Assignment
44
PCMOUT
O
PCM Data Output
45
XSYNC
I
Transmit Synchronizing Clock Input
46
RSYNC
I
Receive Synchronizing Clock Input
47
RESET
I
Reset for Control Register
48
N.C
— (Leave unconnected)
49
N.C
— (Leave unconnected)
50
PDN
I
Power-down Control
51
TEST
I
LSI Manufacturer’s Test Input (keep logic “0”)
52
DG
— Digital Ground
53
BSEL1
O
Output for SLIC1 Battery Select
54
ALM1
I
Input from SLIC1 Thermal Shut Down Alarm Detector
55
DET1
I
Input from SLIC1 Switch Hook, Ground Key or Ring Trip Detector
56
E0_1
O
Output for SLIC1 Detector Mode Selection
57
F0_1
O
Mode Control Output to SLIC1 F0
58
F1_1
O
Mode Control Output to SLIC1 F1
59
F2_1
O
Mode Control Output to SLIC1 F2
60
SWC1
O
Output for SLIC1 Uncommitted Switch Control
61
VDDD
— Power Supply for Internal Digital Circuit
62
VDDA
— Power Supply for Internal Analog Circuit
63
AIN1P
I
CH1 Transmit Op-amp Input Positive
64
N.C
— (Leave unconnected)
Note: In this datasheet, “1” and “2” in names for pins which respectively exist for CH1 and CH2 are often
substituted by “n” (in a small letter).
Ex) GSX1, GSX2
AOUT1N, AOUT2N
DET1, DET2
→ GSXn
→ AOUTnN
→ DETn
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