1Semiconductor
ML7021
AC Characteristics
Parameter
Symbol
Clock Frequency
When Internal Sync Signal is not used fC
Clock Cycle Time
When Internal Sync Signal is not used tMCK
Clock Duty Ratio
tDMC
Clock High Level Pulse Width
fc = 19.2 MHz
tMCH
Clock Low Level Pulse Width
fc = 19.2 MHz
tMCL
Clock Rise Time
tr
Clock Fall Time
tf
Sync Clock Output Time
tDCM
Internal Sync Clock Frequency
fCO
Internal Sync Clock Output Cycle Time tCO
Internal Sync Clock Duty Ratio
tDCO
Internal Sync Signal Output Delay Time tDCC
Internal Sync Signal Period
tCYO
Internal Sync Signal Output Width tWSO
Transmit/receive Operation Clock Frequency fSCK
Transmit/receive Sync Clock Cycle Time tSCK
Transmit/receive Sync Clock Duty Ratio tDSC
Transmit/receive Sync Signal Period tCYC
Sync Timing
tXS
tSX
Sync Signal Width
tWSY
Receive Signal Setup Time
tDS
Receive Signal Hold Time
tDH
Receive Data Input Time
tID
IRLD Signal Output Delay Time
tDIC
IRLD Signal Output Width
tWIR
Serial Output Delay Time
tSD
tXD
Reset Signal Input Width
tWR
Reset Start Time
tDRS
Reset End Time
tDRE
Processing Operation Start Time tDIT
VDD = 2.7 V to 3.6 V
Min. Typ. Max.
—
19.2
—
17.5
—
20
— 52.08 —
50
— 57.14
40
—
60
20.8
—
31.3
20.8
—
—
—
—
—
—
—
—
—
64
0.488
40
123
45
45
tSCK
45
45
—
—
—
—
—
1
5
—
100
—
31.3
—
—
—
256
3.9
50
—
125
tCO
—
—
50
125
—
—
—
—
—
7tSCK
—
tSCK
—
—
—
—
—
—
5
5
30
—
—
—
5
—
—
2048
15.6
60
—
—
tCYC-tSCK
—
—
—
138
—
90
90
—
—
52
—
(Ta = –40˚C to +85˚C)
VDD = 4.5 V to 5.5 V
Unit
Min. Typ. Max.
—
19.2
17.5
—
—
MHz
20
— 52.08 —
ns
50
— 57.14
40
—
60
ns
20.8
—
31.3 ns
20.8
—
—
—
—
—
—
—
—
—
64
0.488
40
123
45
45
tSCK
45
45
—
—
—
—
—
1
5
—
100
—
31.3 ns
—
—
—
256
3.9
50
—
125
tCO
—
—
50
125
—
—
—
—
—
7tSCK
—
tSCK
—
—
—
—
—
—
5
ns
5
ns
30
ns
— kHz
—
ms
—
%
5
ns
—
ms
—
ms
2048 kHz
15.6 ms
60
%
—
ms
—
ns
ns
tCYC-tSCK ms
—
ns
—
ns
—
ms
138 ns
—
ms
90
ns
90
ns
—
ms
—
ns
52
ns
—
ms
10