¡ Semiconductor
ML7005
FUNCTIONAL DESCRIPTION
Oscillation Circuit
The X1 and X2 should be connected by a 3.579545 MHz crystal.
When the load capacitance of the crystal is 16pF, X1 and GND should be connected by a 20 pF
capacitor, and X2 and GND also should be connected by a 20 pF capacitor.
If necessary, an external clock should be input to X1 via a 1000 pF capacitor, and X2 should be
left open.
C1
X1
3.579545MHz
X1
3.579545MHz
X2
X2
C2
Figure 6 Crystal Connection
Figure 7 External Clock Connection
DTMF Receiver, CPT Detector Input Level Adjustment
Adjust the input level according to the method shown in the figure 8.
Determine the value of a usable resistor so that the levels of the outputs (DTIO, CPDIO) of each
amplifier at a maximum input level are less than the maximum detect level described in the AC
Characteristics.
CA
IN
DTRIP
DTRIM
(CPDIP)
+
–
(CPDIM)
DTRIO (CPDIO)
RB
RA
RC
SG
RA ≥ 100 kW
RB, RC ≥ 50 kW
CA ≥ 0.1 mF
Gain = 1 + RB £ 10
RC
CA RD
IN
DTRIO
RE
(CPDIO)
DTRIM
DTRIP
SG
(CPDIM)
–
+
(CPDIP)
Gain = RE £ 10
RD
Figure 8 DTMF, CPT Input Level Adjustment
19/24