ML2724 Просмотр технического описания (PDF) - Micro Linear Corporation

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производитель

ML2724

2.4GHz Low-IF 1.5Mbps FSK Transceiver

Micro Linear Corporation 

ML2724

MODE CONTROL AND INTERFACE LINES

1 XCEN

I (CMOS)

Enables the bandgap reference and

voltage regulators when high. Consumes

only leakage current in STANDBY mode

when low. This is a CMOS input, and the

thresholds are referenced to VDD and

VSS.

2 RXON

I (CMOS)

TX/RX Control Input. Switches the

transceiver between TRANSMIT and

RECEIVE modes. Circuits are powered

up and signal paths reconfigured

according to the operating mode. This is

a CMOS input, and the thresholds are

referenced to VDD and VSS.

XCEN 1

RXON 2

DIN 30

3 PAON

O (CMOS)

PA Control Output. Enables the off-chip

PA at the correct times in a Transmit slot.

Goes high when transmit RF is present

at TXO; goes low 5μs before transmit RF

is removed from TXO. Has interlock logic

to shut down the PA if the PLL does not

lock.

VDD

31

8

VSS

VDD

31

3 PAON

9 FREF

I

Input for the 12.288MHz or 6.144MHz

reference frequency. This input is used

as the reference frequency for the PLL

and as a calibration frequency for the on-

chip filters. An AC-coupled sine or

square wave source drives this self-

biased input.

8 VSS

VCCA

24

9

FREF

40k

11 QPO

O

Charge Pump Output of the phase

detector. This is connected to the

external PLL loop filter.

40k

8

VSS

RVPLL

10

11 QPO

DS2724-F-03

FINAL DATASHEET

8

VSS

DECEMBER 2005 10

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