MK41T56 Просмотр технического описания (PDF) - STMicroelectronics
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MK41T56 Datasheet PDF : 15 Pages
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MK41T56, MKI41T56
WRITE MODE
In this mode the master transmitter transmits to the
MK41T56 slave receiver. Bus protocol is shown in
Figure 10. Following the START condition and
slave address, a logic ’0’ (R/W = 0) is placed on the
bus and indicates to the addressed device that
word address An will follow and is to be written to
the on-chip address pointer. The data word to be
written to the memory is strobed in next and the
internal address pointer is incremented to the next
memory location within the RAM on the reception
of an acknowledge clock. The MK41T56 slave
receiver will send an acknowledge clock to the
master transmitter after it has received the slave
address and again after it has received the word
address and each data byte (see Figure 9).
READ MODE
In this mode, the master reads the MK41T56 slave
after setting the slave address (see Figure 11).
Following the write mode control bit (R/W = 0) and
the acknowledge bit, the word address An is written
to the on-chip address pointer. Next the START
condition and slave address are repeated, followed
by the READ mode control bit (R/W = 1). At this
point, the master transmitter becomes the master
receiver. The data byte which was addressed will
be transmitted and the master receiver will send an
acknowledge bit to the slave transmitter. The ad-
dress pointer is only incremented on reception of
an acknowledge bit. The MK41T56 slave transmit-
ter will now place the data byte at address An + 1
on the bus. The master receiver reads and acknow-
Figure 9. Slave Address Location
START
R/W
SLAVE ADDRESS
A
ledges the new byte and the address pointer is
incremented to An + 2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
An alternate READ mode may also be imple-
mented, whereby the master reads the MK41T56
slave without first writing to the (volatile) address
pointer. The first address that is read is the last one
stored in the pointer, see Figure 12.
CLOCK CALIBRATION
The MK41T56 is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz. A
typical MK41T56 is accurate within ± 1 minute per
month at 25°C without calibration. The devices are
tested not to exceed 35 ppm (parts per million)
oscillator frequency error at 25°C, which equates
to about ± 1.53 minutes per month. The oscillation
rate of any crystal changes with temperature (see
Figure 14).
Most clock chips compensate for crystal frequency
and temperature shift error with cumbersome trim
capacitors. The MK41T56 design, however, em-
ploys periodic counter correction. The calibration
circuit adds or subtracts counts from the oscillator
divider circuit at the divide by 256 stage, as shown
in Figure 13. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value between 0 and 31 in binary
form. The sixth bit is a sign bit; ’1’ indicates positive
calibration, ’0’ indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary ’1’ is loaded into
the register, only the first 2 minutes in the 64
minutes cycle will be modified; if a binary 6 is
loaded, the first 12 will be affected, and so on.
11 0100 0
AI00590
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