MK41T56 Просмотр технического описания (PDF) - STMicroelectronics

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производитель

MK41T56

512 bit (64b x8) Serial Access TIMEKEEPER® SRAM

STMicroelectronics 

Figure 3. Block Diagram

OSCI

OSCO

FT/OUT

VCC

VSS

VBAT

OSCILLATOR

32.768 kHz

VOLTAGE

SENSE

and

SWITCH

CIRCUITRY

SCL

SDA

SERIAL

BUS

INTERFACE

MK41T56, MKI41T56

DIVIDER

CONTROL

LOGIC

1 Hz

SECONDS

MINUTES

HOURS

DAY

DATE

MONTH

YEAR

CONTROL

ADDRESS

REGISTER

RAM

(56 x 8)

AI00586C

DESCRIPTION (cont’d)

Data retention time is in excess of 10 years with a

50mAh 3V lithium cell. The MK41T56 is supplied in

8 pin Plastic Dual-in-Line and 8 lead Plastic SOIC

packages.

OPERATION

The MK41T56 clock operates as a slave device on

the serial bus. Access is obtained by implementing

a start condition followed by the correct slave ad-

dress (11010000). The 64 bytes contained in the

device can then be accessed sequentially in the

following order:

1.

Seconds Register

2.

Minutes Register

3.

Hours Register

4.

Day Register

5.

Date Register

6.

Month Register

7.

Years Register

8.

Control Register

9 to 64. RAM

Table 4. AC Measurement Conditions

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no

longer driven.

Figure 4. AC Testing Load Circuit

5V

DEVICE

UNDER

TEST

1kΩ

1.8kΩ

OUT

CL = 100pF

CL includes JIG capacitance

AI01019

3/15

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