MICRF219AYQS(2009) Просмотр технического описания (PDF) - Micrel

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Компоненты Описание

производитель

MICRF219AYQS
(Rev.:2009)

300MHz to 450MHz ASK Receiver with RSSI, Auto-Poll, Bit-Check and Squelch

Micrel 

Micrel

MICRF219

Parameter

Condition

Min

Typ Max Units

Reference Oscillator

Bias Voltage

RO2

1.15

V

Reference Oscillator

Input Range

0.2

1.5 Vp-p

Reference Oscillator

Source Current

V(REFOSC) = 0V

300

µA

Demodulator

CTH Source

Impedance

CTH Leakage Current

Demodulator Filter

Bandwidth @ 315MHz

FREFOSC = 9.81563 MHz

FREFOSC = 13.52127MHz

TA = 25ºC

TA = +105ºC

Programmable, see application section

165

kΩ

120

±2

nA

± 800

nA

1170

9400 Hz

Demodulator Filter

Programmable, see application section

Bandwidth @ 434MHz

1625

13000 Hz

Digital / Control Functions

DO pin output current As output source @ 0.8 Vdd

sink @ 0.2 Vdd

260

µA

600

Output rise and fall times CI = 15pF, pin DO, 10-90%

2

µsec

Input High Voltage

Pins SCLK, DO (As input), SHDN,SEL0,

SEL1,SQ

0.8Vdd

V

Input Low Voltage

Pins SCLK, DO (As input), SHDN, SEL0,

SEL1,SQ

0.2Vdd V

Output Voltage High DO

0.8Vdd

V

Output Voltage Low DO

0.2Vdd V

RSSI

RSSI DC Output

Voltage Range

-100dBm

-40dBm

0.4

V

2.0

RSSI response slope -110dBm to -40dBm

25

mV/dB

RSSI Output Current

400

µA

RSSI Output Impedance

250

Ω

RSSI Response Time 50% data duty cycle, input power to

Antenna = -20dBm

0.3

sec

Note 1.

Note 2.

Note 3.

Note 4.

Note 5.

Exceeding the absolute maximum rating may damage the device.

The device is not guaranteed to function outside of its operating rating.

Device is ESD sensitive. Use appropriate ESD precautions. Exceeding the absolute maximum rating may damage the device.

Sensitivity is defined as the average signal level measured at the input necessary to achieve 10-2 BER (bit error rate). The input signal is

defined as a return-to-zero (RZ) waveform with 50% average duty cycle (Manchester encoded) at a data rate of 1kbps.

When data burst does not contain preamble, duty cycle is defined as total duty cycle, including any “quiet” time between data bursts. When

data bursts contain preamble sufficient to charge the slice level on capacitor CTH, then duty cycle is the effective duty cycle of the burst

alone. [For example, 100msec burst with 50% duty cycle, and 100msec “quiet” time between bursts. If burst includes preamble, duty

cycle is TON/(TON+tOFF)= 50%; without preamble, duty cycle is TON/(TON+ TOFF + TQUIET) = 50msec/(200msec)=25%. TON is the (Average

number of 1’s/burst) × bit time, and TOFF = (TBURST – TON.)

January 2009

4

M9999-011509

(408) 944-0800

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