MICRF011 Просмотр технического описания (PDF) - Micrel

Номер в каталоге

Компоненты Описание

производитель

MICRF011

QwikRadio Receiver/Data Demodulator

Micrel 

MICRF011

QwikRadio tm

Micrel

3. Selecting CAGC Capacitor

Selection of CAGC is dictated by minimizing the ripple on

the AGC control voltage, by using a sufficiently large

capacitor. It is Micrel’s experience that CAGC should be in

the vicinity of 0.47µF to 4.7µF. Large capacitor values

should be carefully considered, as this determines the time

required for the AGC control voltage to settle from a

completely discharged condition. AGC settling time from a

completely discharged (0-volt) state is given approximately

by equation (6):

capacitor CAGC. The attack current is nominally 15µA,

while the decay current is a 1/10th scaling of this,

approximately 1.5µA. Signal gain of the RF/IF strip inside

the IC diminishes as the voltage on CAGC decreases. By

simply adding a capacitor to CAGC pin, the attack/decay

time constant ratio is fixed at 1:10. Further discussion on

setting the attack time constant is found in “Application Note

22, MICRF001 Theory of Operation”, section 6.5.

Modification of the attack/decay ratio is possible by adding

resistance from CAGC pin either to VDDBB or VSSBB, as

desired.

∆T = (1.333 * CAGC) – 0.44

(6)

4. DO Pin

where CAGC is in microfarads, and ∆T is in seconds.

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF011 is

shown in Figures 1 through 6. Specific information

regarding each of these circuits is discussed in the following

sub-paragraphs. Not shown are ESD protection diodes

which are applied to all input and output pins.

1. ANT Pin

The ANT pin is internally AC-coupled via a 3pF capacitor, to

The output stage for the Data Comparator (DO pin) is shown

in Figure 4. The output is a 10µA push-10µA pull, switched

current stage. Such an output stage is capable of driving

CMOS-type loads.

An external buffer-driver is

recommended for driving high capacitance loads.

5. REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input

impedance is quite high (200kΩ). This is a Colpitts

oscillator, with internal 30pF capacitors. This input is

intended to work with standard ceramic resonators,

connected from this pin to VSSBB, although a crystal may

be used instead, where greater frequency accuracy is

required. The resonators should not contain integral

capacitors, since these capacitors are contained inside the

IC. Externally applied signals should be AC-coupled,

amplitude limited to approximately 0.5Vpp. The nominal DC

bias voltage on this pin is 1.4V.

6. Control Inputs (SEL0, SEL1, SWEN)

Figure 1 ANT Pin

an RF N-channel MOSFET, as shown in Figure 1.

Impedance on this pin to VSS is quite high at low

frequencies, and decreases as frequency increases. In the

UHF frequency range, the device input can be modeled as

6.3kΩ in parallel with 2pF (pin capacitance) shunt to

VSSRF.

Control input circuitry is shown in Figure 6. The standard

input is a logic inverter constructed with minimum geometry

MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a large

channel length device which functions essentially as a

“weak” pullup to VDDBB. Typical pullup current is 5µA,

leading to an impedance to the VDDBB supply of typically

1MΩ.

2. CTH Pin

Figure 2 illustrates the CTH pin interface circuit. CTH pin is

driven from a P-channel MOSFET source-follower biased

with approximately 10µA of bias current. Transmission

gates TG1 and TG2 isolate the 6.9pF capacitor. Internal

control signals PHI1/PHI2 are related in a manner such that

the impedance across the transmission gates looks like a

“resistance” of approximately 118kΩ. The DC potential on

the CTH pin is approximately 1.6V.

3. CAGC Pin

Figure 3 illustrates the CAGC pin interface circuit. The AGC

control voltage is developed as an integrated current into a

December 1998b

99

MICRF011

Share Link: