MICRF007BM Просмотр технического описания (PDF) - Micrel

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MICRF007BM

QwikRadio® Low-Power UHF Receiver

Micrel 

MICRF007

Inductor values may be different from Table 4, depending

on PCB material, PCB thickness, ground configuration, and

how long the traces are in the layout. Values shown were

charac-terized for a 0.031 inch thickness, FR4 board, solid

ground plane on bottom layer, and very short traces. Murata

and Coilcraft wire-wound 0603 or 0805 surface mount induc-

tors were tested, however, any wire-wound inductor with high

SRF (self-resonance frequency) should do the job.

Shutdown Function

Duty-cycled operation of the MICRF007 (often referred to

as polling) is achieved by turning the MICRF007 on and off

via the SHUT pin. The shutdown function is controlled by a

logic state applied to the SHUT pin. When VSHUT is high, the

device goes into low-power standby mode. This pin is pulled

high internally, it must be externally pulled low to enable the

receiver. It is recommended to connect this pin through a

100kΩ resistor to ground

Power Supply Bypass Capacitors

Power supply bypass capacitor(s) connected to VDD should

have the shortest possible lead lengths to VSS.

Increasing Selectivity with Optional Band-Pass Filter

For applications located in high ambient noise environments,

a fixed value band-pass network may be connected between

the ANT pin and VSS to provide additional receiver selectivity

and input overload protection. A minimum input configura-

tion is included in Figure 10. It provides some filtering and

necessary overload protection.

Data Squelching

During quiet periods (no signal), the data output (DO pin)

transitions randomly with noise. Most decoders can discrimi-

nate between this random noise and actual data. But for some

system, it does present a problem. There are three possible

approaches to reduce this output noise:

1. Analog squelch to raise the demodulator threshold

2. Digital squelch to disable the output when data is not

present

3. Output filter to filter the (high frequency) noise glitches

on the data output pin.

The simplest solution is to add analog squelch by introduc-

ing a small offset, or squelch voltage, on the CTH pin so that

noise does not trigger the internal comparator. Usually 20mV

to 30mV is sufficient, and may be achieved by connecting

a several-meg-ohm resistor from the CTH pin to either VSS

or VDD, depending on the desired offset polarity. Since

MICRF007’s receiver AGC noise at the internal comparator

input is always the same (set by the AGC), the squelch offset

requirement does not change as the local noise strength

changes from installation to installation. Introducing squelch

will reduce sensitivity and also reduce range. Only introduce

an amount of offset sufficient to quiet the output. Typical

squelch resistor values range from 10MΩ to 6.8MΩ for low

to high squelch strength.

Micrel

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF007

are diagrammed in Figures 4 through 9. The ESD protection

diodes at all input and output pins are not shown.

ANT Pin

50 3pF

Active

Load

6k

Active

Bias

Figure 4. ANT Pin

The ANT pin is internally AC-coupled via a 3pF capacitor to

an RF N-Channel MOSFET, as shown in Figure 4. Im-ped-

ance on this pin to VSS is quite high at low frequencies, and

decreases as frequency increases. In the UHF fre-quency

range, the device input can be modeled as 6.3k. in parallel

with 2pF (pin capacitance) to VSS.

CTH Pin

VDD

1.5A

Compa-

rator

67.5A

CAGC

Timout

15FAigure 5. C6T75HAPin

Figure 5 illustrates the CTH-pin interface circuit. The CTH

pin is driven from

with approximately

a10Pµ-ACVhSoSaf nbniaesl .MTOraSnFsmETisssioounrcgea-tfeoslloTwGe1r

and TG2 isolate the 6.9pF capacitor. Internal control signals

PHI1/PHI2 are related in a manner such that the impedance

across the transmission gates looks like a “resistance” of

approximately 110kΩ. The DC potential at the CTH pin is

approximately 1.6V

CAGC Pin

Figure 6 illustrates the CAGC pin interface circuit. The AGC

control voltage is developed as an integrated current into a

capacitor CAGC. The attack current is nominally 1.5µA, while

the decay current is a 10 times scaling of this, approximately

15µA. Signal gain of the RF/IF strip inside the IC diminishes

as the voltage on CAGC decreases. By simply adding a

capacitor to CAGC pin, the attack/decay time constant ratio

is fixed at 10:1. Modification of the attack/decay ratio is pos-

sible by adding resistance from the CAGC pin to either VDD

or VSS, as desired.

Both the push and pull current sources are disabled during

shutdown, which maintains the voltage across CAGC, and

improves recovery time in duty-cycled applications. To further

improve duty-cycle recovery, both push and pull currents are

increased by 45 times for approximately 10ms after release

of the SHUT pin. This allows rapid recovery of any voltage

drop on CAGC while in shutdown.

February 17, 2005

9

M9999-021705

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