MICRF005 Просмотр технического описания (PDF) - Micrel

Номер в каталоге

Компоненты Описание

производитель

MICRF005

115kbps, 800MHz - 1GHz UHF Receiver

Micrel 

MICRF005

duty-cycled operation. The actual tolerable leakage will be

application dependent. Clearly, leakage performance is less

critical when the device off-time is low (milliseconds) and

more critical when the off-time is high (seconds).

To further enhance duty-cycled operation of the IC, the AGC

push and pull currents are increased for a fixed time immedi-

ately after the device is taken out of shutdown mode (turned-

on). This compensates for AGC capacitor voltage droop

while the IC is in shutdown mode, reduces the time to restore

the correct AGC voltage, and therefore extends maximum

achievable duty ratios. Push-pull currents are increased by

45 times their nominal values. The fixed time period is based

on the reference oscillator frequency fT, [tbd]ms for fT =

14.3359MHz, and varies inversely as fT varies.

Transmit / Standby Function

The transmit/receive function is controlled by the logic state

of T/R. T/R is internally tied to VSS. When T/R is open circuit

or in the low state, the MICRF005 functions in its normal

receive operating mode. The T/R pin may be pulled high to

Vdd, this will place the receiver in a “stand-by” operating

mode. This mode is intended for use during transmit cycles

in transceiver applications where the receiver is co-located

with a transmitter. In this “transmit” mode, the receiver

oscillator remains active but the AGC function is disabled and

the CAGC pin is high impedance to hold the AGC capacitor

voltage. This function enables the MICRF005 to immediately

resume receive operation after a transmit cycle.

Shutdown Function

The shutdown function is controlled by a logic state applied

to the SHUT pin. When VSHUT is high, the device goes into

low-power standby mode, consuming less than 1µA. This pin

is pulled high internally. It must be externally pulled low to

enable the receiver.

Reference Oscillator

All timing and tuning operations on the MICRF005 are de-

rived from the internal Colpitts reference oscillator. Timing

and tuning is controlled through the REFOSC pin in one of two

ways:

1. Connect a crystal

2. Drive this pin with an external timing signal

The second approach is attractive for lowering system cost

further if an accurate reference signal exists elsewhere in the

system, for example, a reference clock from a crystal-con-

trolled microprocessor. An externally applied signal should

be ac-coupled and resistively-attenuated, or otherwise lim-

ited, to approximately 0.5Vpp. The specific reference fre-

quency required is related to the system transmit frequency.

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF005

are diagrammed in Figures 1 through 6. The ESD protection

diodes at all input and output pins are not shown. Integrated

into an actual design application with the best results pos-

sible.

CTH Pin

VDDBB

Micrel

Demodulator

Signal

2.85Vdc

PHI2B

PHI1B

CTH

6.9pF

PHI2

PHI1

VSSBB

VSSBB

Figure 2. CTH Pin

Figure 2 illustrates the CTH-pin interface circuit. The CTH pin

is driven from a P-channel MOSFET source-follower with

approximately 10µA of bias. Transmission gates TG1 and

TG2 isolate the 6.9pF capacitor. Internal control signals

PHI1/PHI2 are related in a manner such that the impedance

across the transmission gates looks like a “resistance” of

approximately 100kΩ. The dc potential at the CTH pin is

approximately 1.6V

CAGC Pin

VDDBB

1.5µA

Compa-

rator

67.5µA

CAGC

Timout

15µA

675µA

VSSBB

Figure 3. CAGC Pin

Figure 3 illustrates the CAGC pin interface circuit. The AGC

control voltage is developed as an integrated current into a

capacitor CAGC. The attack current is nominally 15µA, while

the decay current is a 1/10th scaling of this, nominally 1.5µA,

making the attack/decay timeconstant ratio a fixed 10:1.

Signal gain of the RF/IF strip inside the IC diminishes as the

voltage at CAGC decreases. Modification of the attack/decay

ratio is possible by adding resistance from the CAGC pin to

either VDDBB or VSSBB, as desired.

Both the push and pull current sources are disabled during

shutdown, which maintains the voltage across CAGC, and

improves recovery time in duty-cycled applications. To fur-

ther improve duty-cycle recovery, both push and pull currents

are increased by 45 times for approximately 10ms after

release of the SHUT pin. This allows rapid recovery of any

voltage droop on CAGC while in shutdown.

MICRF005

6

October 2001

Share Link: