MICRF004 Просмотр технического описания (PDF) - Micrel

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MICRF004

QwikRadio™ Low-Power VHF Receiver

Micrel 

MICRF004/RF044

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF004

are diagrammed in Figures 1 through 6. The ESD protection

diodes at all input and output pins are not shown.

ANT Pin

Active

Load

3pF

ANT

50

6k

Active

Bias

Figure 1. ANT Pin

The ANT pin is internally ac-coupled, through a 3pF capaci-

tor, to an RF N-channel MOSFET, as shown in Figure 1.

Impedance from this pin to VSS is high at low frequencies and

decreases as frequency increases. In the VHF frequency

range, the device input can be modeled as a 6.3kΩ in parallel

with 2pF (pin capacitance) shunt to the VSSRF pin.

CTH Pin

VDDBB

Demodulator

Signal

2.85Vdc

PHI2B

PHI1B

CTH

6.9pF

VSSBB PHI2 VSSBB PHI1

Figure 2. CTH Pin

Figure 2 illustrates the CTH-pin interface circuit. The CTH pin

is driven from a P-channel MOSFET source-follower with

approximately 10µA of bias. Transmission gates TG1 and

TG2 isolate the 6.9pF capacitor. Internal control signals

PHI1/PHI2 are related in a manner such that the impedance

across the transmission gates looks like a “resistance” of

approximately 100kΩ. The dc potential at the CTH pin is

approximately 1.6V

CAGC Pin

VDDBB

1.5µA

Compa-

rator

67.5µA

CAGC

Timout

15µA

675µA

VSSBB

Figure 3. CAGC Pin

Micrel

Figure 3 illustrates the CAGC pin interface circuit. The AGC

control voltage is developed as an integrated current into a

capacitor CAGC. The attack current is nominally 15µA, while

the decay current is a 1/10th scaling of this, nominally 1.5µA,

making the attack/decay timeconstant ratio a fixed 10:1.

Signal gain of the RF/IF strip inside the IC diminishes as the

voltage at CAGC decreases. Modification of the attack/decay

ratio is possible by adding resistance from the CAGC pin to

either VDDBB or VSSBB, as desired.

Both the push and pull current sources are disabled during

shutdown, which maintains the voltage across CAGC, and

improves recovery time in duty-cycled applications. To fur-

ther improve duty-cycle recovery, both push and pull currents

are increased by 45 times for approximately 10ms after

release of the SHUT pin. This allows rapid recovery of any

voltage droop on CAGC while in shutdown.

DO and WAKEB Pins

VDDBB

Compa-

rator

10µA

DO

10µA

VSSBB

Figure 4. DO and WAKEB Pins

The output stage for DO (digital output) and WAKEB (wakeup

output) is shown in Figure 4. The output is a 10µA push and

10µA pull switched-current stage. This output stage is ca-

pable of driving CMOS loads. An external buffer-driver is

recommended for driving high-capacitance loads.

REFOSC Pin

Active

Bias

VDDBB

REFOSC

30pF

200k

250Ω

30pF

VSSBB

30µA

VSSBB

Figure 5. REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input imped-

ance is high (200kΩ). This is a Colpitts oscillator with internal

30pF capacitors. This input is intended to work with standard

ceramic resonators connected from this pin to the VSSBB

pin, although a crystal may be used when greater frequency

accuracy is required. The nominal dc bias voltage on this pin

is 1.4V.

February 9, 2000

9

MICRF004/RF044

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