AD7701(RevD) Просмотр технического описания (PDF) - Analog Devices
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AD7701 Datasheet PDF : 16 Pages
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AD7701
OFFSET CALIBRATION RANGE
In the system calibration modes (SC2 low) the AD7701
calibrates its offset with respect to the AIN pin. The Offset
Calibration Range specification defines the range of voltages,
expressed as a percentage of VREF that the AD7701 can accept
and still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGE
This is the range of voltages that the AD7701 can accept in the
system calibration mode and still calibrate full-scale correctly.
The AD7701 can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. A calibration cycle may be initiated at any time
using the CAL control input.
Other system components may also be included in the
calibration loop to remove offset and gain errors in the input
channel.
For battery operation, the AD7701 also offers a standby mode
that reduces idle power consumption to typically 10 µW.
INPUT SPAN
In system calibration schemes, two voltages applied in sequence
to the AD7701’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full-scale that the AD7701 can
accept and still calibrate gain accurately. The input span is ex-
pressed as a percentage of VREF.
GENERAL DESCRIPTION
The AD7701 is a 16-bit A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those representing chemical,
physical or biological processes. It contains a charge-balancing
(sigma-delta) ADC, calibration microcontroller with on-chip
static RAM, a clock oscillator and a serial communications port.
The analog input signal to the AD7701 is continuously sampled
at a rate determined by the frequency of the master clock,
CLKIN. A charge-balancing A/D converter (Sigma-Delta
Modulator) converts the sampled signal into a digital pulse train
whose duty cycle contains the digital information. A six-pole
Gaussian digital low-pass filter processes the output of the
modulator and updates the 16-bit output register at a 4 kHz
rate. The output data can be read from the serial port randomly
or periodically at any rate up to 4 kHz.
+5V
ANALOG
SUPPLY
0.1µF
10µF
AVDD
VOLTAGE 2.5V
REFERENCE
VREF
DVDD
SLEEP
MODE
DRDY
RANGE
SELECT
CALIBRATE
ANALOG
INPUT
ANALOG
GROUND
–5V
ANALOG
SUPPLY 0.1µF
0.1µF
CS
BP/UP
SCLK
CAL
SDATA
AD7701
CLKIN
AIN
CLKOUT
SC1
AGND
SC2
DGND
AVSS
DVSS
10µF
0.1µF
DATA
READY
READ
(TRANSMIT)
SERIAL
CLOCK
SERIAL
DATA
0.1µF
THEORY OF OPERATION
The general block diagram of a sigma-delta ADC is shown in
Figure 8. It contains the following elements.
1. A sample-hold amplifier.
2. A differential amplifier or subtracter.
3. An analog low-pass filter.
4. A 1-bit A/D converter (comparator).
5. A 1-bit DAC.
6. A digital low-pass filter.
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the
difference signal at a frequency many times that of the analog
signal sampling frequency (oversampling).
S/H AMP
ANALOG
LOW-PASS
FILTER
COMPARATOR
DIGITAL
FILTER
DAC
DIGITAL DATA
Figure 8. General Sigma-Delta ADC
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
SNR = (6.02 × number of bits + 1.76) dB
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7701 samples the input signal at 16 kHz, which spreads
the quantization noise from 0 to 8 kHz. Since the specified
analog input bandwidth of the AD7701 is only 0 to 10 Hz, the
noise energy in this bandwidth would be only 1/800 of the total
quantization noise, even if the noise energy was spread evenly
throughout the spectrum. It is reduced still further by analog
filtering in the modulator loop, which shapes the quantization
noise spectrum to move most of the noise energy to frequencies
above 10 Hz. The SNR performance in the 0 to 10 Hz range is
conditioned to the 16-bit level in this fashion.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data word using a
digital filter.
Figure 7. Typical System Connection Diagram
REV. D
–7–
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