AD7701(RevD) Просмотр технического описания (PDF) - Analog Devices
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AD7701 Datasheet PDF : 16 Pages
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AD7701
TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V ؎ 10%; AVSS = DVSS = –5 V ؎ 10%; AGND = DGND = O V;
fCLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD)
Limit at TMIN, TMAX Limit at TMIN, TMAX
Parameter (A, B Versions)
(S, T Versions)
Units
Conditions/Comments
fCLKIN3, 4
tr5
tf5
t1
t2
t36
200
5
200
5
50
50
0
50
1000
200
5
200
5
50
50
0
50
1000
kHz min Master Clock Frequency: Internal Gate Oscillator
MHz max Typically 4.096 MHz
kHz min Master Clock Frequency: Externally Supplied
MHz max
ns max Digital Output Rise Time. Typically 20 ns
ns max Digital Output Fall Time. Typically 20 ns
ns min SC1, SC2 to CAL High Setup Time
ns min SC1, SC2 Hold Time After CAL Goes High
ns min SLEEP High to CLKIN High Setup Time
SSC Mode
t47
t5
t6
t7
t8
t98
t108, 9
3/fCLKIN
100
250
300
790
l/fCLKIN +200
(4/fCLKIN) +200
3/fCLKIN
100
250
300
790
l/fCLKIN +200
(4/fCLKIN) +200
ns max
ns max
ns min
ns max
ns max
ns max
ns max
Data Access Time (CS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay (25 ns typ)
MSB Data Setup Time. Typically 380 ns
SCLK High Pulse Width. Typically 240 ns
SCLK Low Pulse Width. Typically 730 ns
SCLK Rising Edge to Hi-Z Delay (l/fCLKIN + 100 ns typ)
CS High to Hi-Z Delay
SEC Mode
fSCLK
5
t11
35
t12
160
t137, 10
160
t1411
150
t158
250
t168
200
5
MHz
Serial Clock Input Frequency
35
ns min SCLK Input High Pulse Width
160
ns min SCLK Low Pulse Width
160
ns max Data Access Time (CS Low to Data Valid). Typically 80 ns
150
ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns
250
ns max CS High to Hi-Z Delay
200
ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns
AC Mode
t17
40
t18
180
t19
200
40
ns min CS Setup Time. Typically 20 ns
180
ns max Data Delay Time. Typically 90 ns
200
ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns
NOTES
11Sample tested at +25°C to ensure compliance. All input signals are specified with t r = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
12See Figures 1 to 6.
13CLKIN Duty Cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
14The AD7701 is production tested with fCLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
15Specified using 10% and 90% points on waveform of interest.
16In order to synchronize several AD7701s together using the SLEEP pin, this specification is met.
17t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
18t9, t10, t15 and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is
then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true bus relinquish time of the part and as such as independent of external bus loading capacitance.
19If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as
great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than
4 CLKIN cycles plus 160 ns after CS goes low.
11SDATA is clocked out on the falling edge of the SCLK input.
REV. D
–5–
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