MT90210 Просмотр технического описания (PDF) - Mitel Networks

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Компоненты Описание

производитель

MT90210

Multi-Rate Parallel Access Circuit

Mitel Networks 

MT90210

Preliminary Information

Frame Boundary Established by F0i

SCLK

(4 MHz)

SCLK

(8 MHz)

SCLK, C16

(16 MHz)

F0i

Serial I/O

2 Mb/s

Ch. 31, Bit 1

Ch. 31, Bit 0

Ch. 0, Bit 7

Ch. 0, Bit 6

Serial I/O

4 Mb/s

Serial I/O

8 Mb/s

Ch. 63, Bit 2

Ch. 63, Bit 1

Ch. 63, Bit 0

Ch. 0, Bit 7

Ch. 0, Bit 6

Ch. 0, Bit 5

Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 0, Ch. 0, Ch. 0, Ch. 0, Ch. 0, Ch. 0,

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

Figure 6 - Serial Port Functional Timing

last write address

of frame n

W

A0-A12

R

I

P0-P7

T

Data

Out

E

WBC

address x

Data

Out

inactive

inactive

MT90210 finishes writing

data from frame n.

MT90210 will handle parallel port

transactions related to frame n +1.

last read address

of frame n

A0-A12

R

address y

E

A

P0-P7

D

Data

In

Data

In

WBC

inactive

inactive

MT90210 finishes reading

data from frame n.

MT90210 will handle parallel port

transactions related to frame n +1.

Figure 7a - WBC and RBC Output Transition

2-152

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