MCP1640(2015) Просмотр технического описания (PDF) - Microchip Technology

Номер в каталоге

Компоненты Описание

производитель

MCP1640
(Rev.:2015)

0.65V Start-Up Synchronous Boost Regulator with True Output Disconnect or Input/Output Bypass Option

Microchip Technology 

MCP1640/B/C/D

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP1640/B/C/D

2x3 DFN

MCP1640/B/C/D

SOT-23

Symbol

Description

1

4

VFB Feedback Voltage Pin

2

—

SGND Signal Ground Pin

3

—

PGND Power Ground Pin

4

3

EN Enable Control Input Pin

5

1

SW Switch Node, Boost Inductor Input Pin

6

—

VOUTP Output Voltage Power Pin

7

—

VOUTS Output Voltage Sense Pin

8

6

VIN Input Voltage Pin

9

—

EP Exposed Thermal Pad (EP); must be connected to VSS

—

2

GND Ground Pin

—

5

VOUT Output Voltage Pin

3.1 Feedback Voltage Pin (VFB)

The VFB pin is used to provide output voltage regulation

by using a resistor divider. Feedback voltage will be

1.21V typical with the output voltage in regulation.

3.2 Signal Ground Pin (SGND)

The signal ground pin is used as a return for the

integrated VREF and error amplifier. In the 2x3 DFN

package, the SGND and power ground (PGND) pins are

connected externally.

3.3 Power Ground Pin (PGND)

The power ground pin is used as a return for the

high-current N-Channel switch. In the 2x3 DFN

package, the PGND and SGND pins are connected

externally.

3.4 Enable Pin (EN)

The EN pin is a logic-level input used to enable or

disable device switching and lower quiescent current

while disabled. A logic high (>90% of VIN) will enable

the regulator output. A logic low (<20% of VIN) will

ensure that the regulator is disabled.

3.5 Switch Node Pin (SW)

Connect the inductor from the input voltage to the SW

pin. The SW pin carries inductor current and can be as

high as 800 mA peak. The integrated N-Channel switch

drain and integrated P-Channel switch source are

internally connected at the SW node.

3.6 Output Voltage Power Pin (VOUTP)

The output voltage power pin connects the output

voltage to the switch node. High current flows through

the integrated P-Channel and out of this pin to the

output capacitor and the output. In the 2x3 DFN

package, VOUTP and VOUTS are connected externally.

3.7 Output Voltage Sense Pin (VOUTS)

The output voltage sense pin connects the regulated

output voltage to the internal bias circuits. In the

2x3 DFN package, the VOUTS and output voltage

power (VOUTP) pins are connected externally.

3.8 Power Supply Input Voltage Pin (VIN)

Connect the input voltage source to VIN. The input

source should be decoupled to GND with a 4.7 µF

minimum capacitor.

3.9 Exposed Thermal Pad (EP)

There is no internal electrical connection between the

Exposed Thermal Pad (EP) and the SGND and PGND

pins. They must be connected to the same potential on

the Printed Circuit Board (PCB).

3.10 Ground Pin (GND)

The ground or return pin is used for circuit ground

connection. Length of trace from input cap return,

output cap return, and GND pin should be made as

short as possible to minimize noise on the GND pin. In

the SOT-23-6 package, a single ground pin is used.

3.11 Output Voltage Pin (VOUT)

The output voltage pin connects the integrated

P-Channel MOSFET to the output capacitor. The FB

voltage divider is also connected to the VOUT pin for

voltage regulation.

 2010-2015 Microchip Technology Inc.

DS20002234D-page 9

Share Link: