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MCF5275LCVM133

Integrated Microprocessor Family Hardware Specification

Freescale Semiconductor 

Signal Descriptions

Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate1 Alternate2 Dir.1

MCF5274

MCF5275

MCF5274L

MCF5275L

256 MAPBGA 196 MAPBGA

FEC1_TXD[3:1] PFEC1L[7:5]

—

—

O E1, E2, F2

—

FEC1_TXER PFEC1L[4]

—

—

O

D1

—

FEC1_RXD[3:1] PFEC1L[3:1]

—

—

I

B1, B2, A2

—

FEC1_RXER PFEC1L[0]

—

—

I

C2

—

I2C

I2C_SDA

PFECI2C[1] U2RXD

—

I/O

B10

B7

I2C_SCL

PFECI2C[0] U2TXD

—

I/O

C10

A7

DMA

DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads.

—

—

Please refer to the following pins for muxing:

PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for

DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for

DREQ2, TEA for DREQ1, and TIP for DREQ0.

QSPI

QSPI_CS[3:2]

QSPI_CS1

QSPI_CS0

QSPI_CLK

QSPI_DIN

QSPI_DOUT

PQSPI[6:5]

PQSPI[4]

PQSPI[3]

PQSPI[2]

PQSPI[1]

PQSPI[0]

PWM[3:2] DACK[3:2] O

—

—

O

—

—

O

I2C_SCL

—

O

I2C_SDA

—

I

—

—

O

R13, N12

T14

P12

T15

T13

R12

P10, N9

N10

M9

L11

M10

L10

UARTs

U2RXD

PUARTH[3]

—

—

I

T9

—

U2TXD

PUARTH[2]

—

—

O

R9

—

U2CTS

PUARTH[1]

PWM1

—

I

P9

—

U2RTS

PUARTH[0]

PWM0

—

O

R8

—

U1RXD

PUARTL[7]

—

—

I

A9

A6

U1TXD

PUARTL[6]

—

—

O

B9

D7

U1CTS

PUARTL[5]

—

—

I

C9

C7

U1RTS

PUARTL[4]

—

—

O

D9

B6

U0RXD

PUARTL[3]

—

—

I

A8

A4

U0TXD

PUARTL[2]

—

—

O

B8

A5

U0CTS

PUARTL[1]

—

—

I

C8

C6

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

7

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