MCF5275LCVM133 Просмотр технического описания (PDF) - Freescale Semiconductor

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MCF5275LCVM133

Integrated Microprocessor Family Hardware Specification

Freescale Semiconductor 

Block Diagram

2 Block Diagram

The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array

(MAPBGA) package.

Figure 1 shows a top-level block diagram of the MCF5275, the superset device.

(To/From SRAM backdoor)

Arbiter

INTC0 INTC1

EIM

CHIP

SELECTS

EBI

(To/From PADI)

FAST ETHERNET

CONTROLLER

(FEC0)

(To/From PADI)

FAST ETHERNET

CONTROLLER

(FEC1)

(To/From

PADI)

4 CH DMA

JTAG

TAP

DREQ[1:0] DACK[3:0]

JTAG_EN

(To/From

PADI)

(To/From PADI)

4 CH PWM

Watchdog

Timer

UART

0

UART UART

1

2

I2C

QSPI

DTIM DTIM DTIM DTIM

0

1

2

3

SDRAMC

V2 ColdFire CPU

DIV

EMAC

64 Kbytes

SRAM

(8Kx16)x4

16 Kbytes

CACHE

(1Kx32)x4

(To/From Arbiter backdoor)

PORTS

(GPIO)

DDR

QSPI

I2C_SDA

I2C_SCL

TXDx

RXDx

RTSx

CTSx

DTOUTx

DTINx

FEC0

FEC1

USB

PWMx

D[31:16]

A[23:0]

R/W

CS[3:0]

TA

JTAG_EN

TRST

TCLK

TMS

TDI

TDO

TSIZ[1:0]

TEA

BS[3:2]

CIM

MDHA RNGA SKHA

USB 2.0

Full Speed

Edge

Port

PLL

CLKGEN

PIT0

PIT1

Cryptography

Modules

(To/From PADI) (To/From INTC)

Figure 1. MCF5275 Block Diagram

PIT2

PIT3

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

3

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