MCF5270 Просмотр технического описания (PDF) - Freescale Semiconductor

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MCF5270

MCF5271 Integrated Microprocessor Hardware Specification

Freescale Semiconductor 

MCF5271 Family Configurations

1 MCF5271 Family Configurations

Table 1. MCF5271 Family Configurations

Module

5270

5271

ColdFire V2 Core with EMAC and

Hardware Divide

x

x

System Clock

100 MHz

Performance (Dhrystone/2.1 MIPS)

96

Instruction/Data Cache

8 Kbytes

Static RAM (SRAM)

64 Kbytes

Interrupt Controllers (INTC)

2

2

Edge Port Module (EPORT)

x

x

External Interface Module (EIM)

x

x

4-channel Direct-Memory Access (DMA)

x

x

SDRAM Controller

x

x

Fast Ethernet Controller (FEC)

x

x

Hardware Encryption

—

x

Watchdog Timer (WDT)

x

x

Four Periodic Interrupt Timers (PIT)

x

x

32-bit DMA Timers

4

4

QSPI

x

x

UART(s)

I2C

3

3

x

x

General Purpose I/O Module (GPIO)

x

x

JTAG - IEEE 1149.1 Test Access Port

x

x

Package

160 QFP,

160 QFP,

196 MAPBGA 196 MAPBGA

2 Block Diagram

The superset device in the MCF5271 family comes in a 196 mold array plastic ball grid array (MAPBGA)

package. Figure 1 shows a top-level block diagram of the MCF5271.

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

2

Freescale Semiconductor

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