M68HC11ERG Просмотр технического описания (PDF) - Motorola => Freescale

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M68HC11ERG

M68HC11E Series Programming Reference Guide

Motorola => Freescale 

Reference Guide

M68HC11ERG/AD

Rev. 2, 10/2003

M68HC11E Series

Programming

Reference Guide

Block Diagram

MODA/ MODB/

LIR VSTBY

XTAL EXTAL E

IRQ XIRQ/VPPE* RESET

MODE CONTROL

OSC

CLOCK LOGIC

INTERRUPT

LOGIC

TIMER

SYSTEM

M68HC11 CPU

PORT A

BUS EXPANSION

ADDRESS

ADDRESS/DATA

STROBE AND HANDSHAKE

PARALLEL I/O

PORT B

CONTROL

PORT C

ROM OR EPROM

(SEE TABLE)

EEPROM

(SEE TABLE)

RAM

(SEE TABLE)

SERIAL

SERIAL

PERIPHERAL COMMUNICATION

VDD

INTERFACE

SPI

INTERFACE

SCI

VSS

CONTROL

PORT D

VRH

VRL

A/D CONVERTER

PORT E

* VPPE applies only to devices with EPROM/OTPROM.

DEVICE

RAM

MC68HC11E0

512

MC68HC11E1

512

MC68HC11E9

512

MC68HC711E9 512

MC68HC11E20 768

MC68HC711E20 768

MC68HC811E2 256

ROM EPROM EEPROM

—

—

—

—

—

512

12 K

—

512

—

12 K

512

20 K

—

512

—

20 K

512

—

—

2048

© Motorola, Inc., 2003

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