MC56F8245 Просмотр технического описания (PDF) - Freescale Semiconductor

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MC56F8245

Digital Signal Controller

Freescale Semiconductor 

Overview

— Maximum ADC clock frequency: up to 10 MHz

– Single conversion time of 8.5 ADC clock cycles (8.5 x 100 ns = 850 ns)

– Additional conversion time of 6-ADC clock cycles (6 x 100 ns = 600 ns)

— Sequential, parallel, and independent scan mode

— First 8 samples have Offset, Limit and Zero-crossing calculation supported

— ADC conversions can be synchronized by eFlexPWM and timer modules via internal crossbar module

— Support for simultaneous and software triggering conversions

— Support for multi-triggering mode with a programmable number of conversions on each trigger

• Inter-module Crossbar Switch (XBAR)

— Programmable internal module connections among the eFlexPWM, ADCs, Quad Timers, 12-bit DAC, HSCMPs,

and package pins

— User-defined input/output pins for PWM fault inputs, Timer input/output, ADC triggers, and Comparator outputs

• Three analog comparators (CMPs)

— Selectable input source includes external pins, internal DACs

— Programmable output polarity

— Output can drive timer input, eFlexPWM fault input, eFlexPWM source, external pin output, and trigger ADCs

— Output falling and rising edge detection able to generate interrupts

— 32-tap programmable voltage reference per comparator

• One 12-bit digital-to-analog converter (12-bit DAC)

— 12-bit resolution

— Power down mode

— Output can be routed to internal comparator, or off chip

• Two four-channel 16-bit multi-purpose timer (TMR) modules

— Four independent 16-bit counter/timers with cascading capability per module

— Up to 120 MHz operating clock

— Each timer has capture and compare and quadrature decoder capability

— Up to 12 operating modes

— Four external inputs and two external outputs

• Two queued serial communication interface (QSCI) modules with LIN slave functionality

— Up to 120 MHz operating clock

— Four-byte-deep FIFOs available on both transmit and receive buffers

— Full-duplex or single-wire operation

— Programmable 8- or 9-bit data format

— 13-bit integer and 3-bit fractional baud rate selection

— Two receiver wakeup methods:

– Idle line

– Address mark

— 1/16 bit-time noise detection

— Support LIN slave operation

• One queued serial peripheral interface (QSPI) module

— Full-duplex operation

— Four-word deep FIFOs available on both transmit and receive buffers

— Master and slave modes

— Programmable length transactions (2 to 16 bits)

— Programmable transmit and receive shift order (MSB as first or last bit transmitted)

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3

6

Freescale Semiconductor

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