MC56F8245 Просмотр технического описания (PDF) - Freescale Semiconductor
Номер в каталоге
Компоненты Описание
производитель
MC56F8245 Datasheet PDF : 88 Pages
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Table of Contents
1 MC56F825x/MC56F824x Family Configuration . . . . . . . . . . . .3
2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 MC56F825x/MC56F824x Features. . . . . . . . . . . . . . . . .4
2.2 Award-Winning Development Environment. . . . . . . . . . .8
2.3 Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . .8
2.4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . .11
3 Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3 MC56F825x/MC56F824x Signal Pins . . . . . . . . . . . . . .18
4 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2 Program Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.3 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.4 Interrupt Vector Table and Reset Vector . . . . . . . . . . . .33
4.5 Peripheral Memory-Mapped Registers . . . . . . . . . . . . .34
4.6 EOnCE Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .35
5 General System Control Information . . . . . . . . . . . . . . . . . . .36
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.2 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.4 On-chip Clock Synthesis . . . . . . . . . . . . . . . . . . . . . . . .37
5.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.6 System Integration Module (SIM) . . . . . . . . . . . . . . . . .39
5.7 Inter-Module Connections. . . . . . . . . . . . . . . . . . . . . . .40
5.8 Joint Test Action Group (JTAG)/Enhanced On-Chip
Emulator (EOnCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.1 Operation with Security Enabled. . . . . . . . . . . . . . . . . .46
6.2 Flash Access Lock and Unlock Mechanisms . . . . . . . .47
6.3 Product Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
7 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
7.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . .48
7.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .49
7.3 ESD Protection and Latch-up Immunity . . . . . . . . . . . .50
7.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .50
7.5 Recommended Operating Conditions . . . . . . . . . . . . . .52
7.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 53
7.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . 55
7.8 Power-On Reset, Low Voltage Detection Specification 56
7.9 Voltage Regulator Specifications . . . . . . . . . . . . . . . . . 56
7.10 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 56
7.11 Enhanced Flex PWM Characteristics . . . . . . . . . . . . . 57
7.12 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . 57
7.13 External Clock Operation Timing. . . . . . . . . . . . . . . . . 57
7.14 Phase Locked Loop Timing . . . . . . . . . . . . . . . . . . . . . 58
7.15 External Crystal or Resonator Requirement . . . . . . . . 59
7.16 Relaxation Oscillator Timing . . . . . . . . . . . . . . . . . . . . 59
7.17 Reset, Stop, Wait, Mode Select, and Interrupt Timing. 60
7.18 Queued Serial Peripheral Interface (SPI) Timing . . . . 60
7.19 Queued Serial Communication Interface (SCI) Timing 64
7.20 Freescale’s Scalable Controller Area Network (MSCAN)65
7.21 Inter-Integrated Circuit Interface (I2C) Timing . . . . . . . 65
7.22 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.23 Quad Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.24 COP Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.25 Analog-to-Digital Converter (ADC) Parameters. . . . . . 68
7.26 Digital-to-Analog Converter (DAC) Parameters . . . . . . 70
7.27 5-Bit Digital-to-Analog Converter (DAC) Parameters. . 71
7.28 HSCMP Specifications . . . . . . . . . . . . . . . . . . . . . . . . 71
7.29 Optimize Power Consumption . . . . . . . . . . . . . . . . . . . 71
8 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . 72
8.2 Electrical Design Considerations. . . . . . . . . . . . . . . . . 73
9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10 Package Mechanical Outline Drawings . . . . . . . . . . . . . . . . . 76
10.1 44-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.2 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Appendix A
Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
2
Freescale Semiconductor
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