33991 Просмотр технического описания (PDF) - Motorola => Freescale

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33991

Gauge Driver Integrated Circuit

Motorola => Freescale 

Freescale Semiconductor, Inc.

STATIC ELECTRICAL CHARACTERISTICS

(Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40° C < TJ < 150° C, unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

SPI Timing Interface

Recommended Frequency of SPI Operation

fSPI

—

1

3

MHz

Falling edge of CS to Rising Edge of SCLK Required Setup Time) (Note9)

TLEAD

—

50

167

ns

Falling edge of SCLK to Rising Edge of CS (Required Setup Time)(Note9)

TLAG

—

50

167

ns

SI to Falling Edge of SCLK (Required Setup Time) (Note9)

TSLSU

—

25

83

ns

Falling Edge of SCLK to SI (Required Hold Time) (Note9)

TSI(HOLD)

—

25

83

ns

SO Rise Time (CL = 200 pF)

TrSO

—

25

50

ns

SO Fall Time (CL = 200 pF)

TfSO

—

25

50

ns

SI, CS, SCLK, Incoming Signal Rise Time (Note10)

TrSI

—

—

50

ns

SI, CS, SCLK, Incoming Signal Fall Time (Note10)

TfSI

—

—

50

ns

Falling Edge of RST to Rising Edge of RST (Required Setup Time) (Note9)

TwRST

—

—

3

µs

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note9)

(Note11)

TCS

—

—

5

µs

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note9)

TEN

—

—

5

µs

Time from Falling Edge of CS to SO Low Impedance (Note12)

TSO(EN)

—

—

145

ns

Time from Rising Edge of CS to SO High Impedance (Note13)

TSO(DIS)

—

1.3

4

µs

Time from Rising Edge of SCLK to SO Data Valid (Note14) 0.2 VDD < = SO

> = 0.8 VDD, CL = 200 pF

TVALID

—

65

105

ns

Notes:

9. The maximum setup times specified for the 33991 is the minimum time needed from the microcontroller to guarantee correct operation.

10. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

11. This value is for a 1 MHz calibrated internal clock; it will change proportionally as the internal clock frequency changes.

12. Time required for output status data to be available for use at SO. 1 K Ω load on SO.

13. Time required for output status data to be terminated at SO. 1 K Ω load on SO.

14. Time required to obtain valid data out from SO following the rise of SCLK.

The device shall meet all SPI interface-timing requirements specified in the SPI Interface Timing, over the temperature range specified in the

environmental requirements section. Digital Interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The

device shall be fully functional for slower clock speeds.

MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfoTArmation On This Product,

Go to: www.freescale.com

33991

9

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