MC33596(2007) Просмотр технического описания (PDF) - Freescale Semiconductor

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MC33596
(Rev.:2007)

PLL Tuned UHF Receiver for Data Transfer Applications

Freescale Semiconductor 

Register Access through SPI

• MISO — (Master Input) Slave Output

Transmits data when slave, with the MSB first. There is no master function. Data are valid on

falling edges of SCLK. This means that the clock phase and polarity control bits of the

microcontroller SPI have to be CPOL = 0 and CPHA = 1 (using Freescale acronyms).

Table 5 summarizes the serial digital interface feature versus the selected mode.

Table 5. Serial Digital Interface Feature versus Selected Mode (SEB = 1)

Selected Mode

MC33596 Digital Interface Use

Configuration

Transmit

Receive DME = 1

DME = 0

Standby / LVD

SPI slave, data received on MOSI, SCLK from MCU, MISO is output

SPI deselected, MOSI receives encoded data from MCU

SPI master, data sent on MOSI with clock on SCLK

SPI deselected, received data are directly sent to MOSI

SPI deselected, all I/O are high impedance

The data transfer protocol for each mode is described in the following sections.

10.2 Configuration Mode

This mode is used to write or read the internal registers of the MC33596.

As long as a low level is applied to CONFB (see Figure 27), the MCU is the master node driving the SCLK

input, the MOSI line input, and the MISO line output. Whatever the direction, SPI transfers are 8-bit based

and always begin with a command byte, which is supplied by the MCU on MOSI. To be considered as a

command byte, this byte must come after a falling edge on CONFB. Figure 3 shows the content of the

command byte.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit Name

N1

N0

A4

A3

A2

A1

A0

R/W

Figure 3. Command Byte

Bits N[1:0] specify the number of accessed registers, as defined in Table 6.

Table 6. Number N of Accessed Registers

N[1:0]

00

01

10

11

Number N of Accessed Registers

1

2

4

8

Bits A[4:0] specify the address of the first register to access. This address is then incremented internally

by N after each data byte transfer.

MC33596 Data Sheet, Rev. 3

10

Freescale Semiconductor

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