MC14093B Просмотр технического описания (PDF) - ON Semiconductor
Номер в каталоге
Компоненты Описание
производитель
MC14093B Datasheet PDF : 9 Pages
| |||
MC14093B
Quad 2−Input NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2−input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Triple Diode Protection on All Inputs
• Pin−for−Pin Compatible with CD4093
• Can be Used to Replace MC14011B
• Independent Schmitt−Trigger at each Input
• Pb−Free Packages are Available
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD Power Dissipation,
per Package (Note 1)
500
mW
TA
Ambient Temperature Range
Tstg Storage Temperature Range
TL
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP−14
P SUFFIX
CASE 646
MARKING
DIAGRAMS
14
MC14093BCP
AWLYYWWG
1
SOIC−14
D SUFFIX
CASE 751A
14
14093BG
AWLYWW
1
TSSOP−14
DT SUFFIX
CASE 948G
14
14
093B
ALYW G
G
1
SOEIAJ−14
F SUFFIX
CASE 965
14
MC14093B
ALYWG
1
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
October, 2006 − Rev. 7
Publication Order Number:
MC14093B/D
Share Link: 