MC14006B Просмотр технического описания (PDF) - Motorola => Freescale
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MC14006B Datasheet PDF : 6 Pages
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#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** When shift register sections are cascaded, the maximum rise and fall times of the clock input should be equal to or less than the rise and fall times
** of the data outputs driving data inputs, plus the propagation delay of the output driving stage for the output capacitance load.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
VDD = – VGS
Vout
14
CLOCK Q4
DP1
Q8
Q9
DP5 Q13
DP10 Q17
DP14 Q18
7 VSS
IOH
EXTERNAL
POWER
SUPPLY
Figure 1. Typical Output Source Current
Characteristics Test Circuit
VDD = VGS
Vout
14
CLOCK Q4
DP1
Q8
Q9
DP5 Q13
DP10 Q17
DP14 Q18
VSS
IOL
EXTERNAL
POWER
SUPPLY
Figure 2. Typical Output Sink Current
Characteristics Test Circuit
MOTOROLA CMOS LOGIC DATA
MC14006B
27
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