MC10ELT24, MC100ELT24
VEE 1
TTL
D2
NC 3
8 VCC
7Q
ECL
6Q
NC 4
5 GND
Figure 1. 8−Lead Pinout (Top View) and Logic
Diagram
Table 1. PIN DESCRIPTION
Pin
Function
Q, Q
ECL Differential Outputs*
D
TTL Input
VCC
VEE
GND
Positive Supply
Negative Supply
Ground
NC
No Connect
EP
Exposed pad must be connected to a sufficient
thermal conduit. Electrically connect to the most
negative supply or leave floating open.
*Output state undetermined when inputs are open.
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
N/A
N/A
> 4 kV
> 200 V
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
51 Devices
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2