MBM29PL160BD Просмотр технического описания (PDF) - Fujitsu

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MBM29PL160BD

16M (2M × 8/1M × 16) BIT

Fujitsu 

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

s FUNCTIONAL DESCRIPTION

Random Read Mode

The MBM29PL160TD/BD has two control functions which must be satisfied in order to obtain data at the outputs.

CE is the power control and should be used for a device selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least tACC - tOE time.) See Figure 5.1 for timing specifications. When reading

out a data without changing addresses after powe-up, it is necessary to input hardware reset or to change CE

pin from "H" to "L".

Page Read Mode

The MBM29PL160TD/BD is capable of fast Page read mode and is compatible with the Page mode MASK ROM

read operation. This mode provides faster read access speed for random locations within a page. The Page size

of the MBM29PL160TD/BD device is 8 words, or 16 bytes, within the appropriate Page being selected by the

higheraddress bits A0 to A2 (in the word mode) and A-1 to A2 (in the byte mode) determining the specific word/

bytewithin that page. This is an asynchronous operation with the microprocessor supplying the specific word or

byte location.

The rondom or initial page access is equal to tACC and subsequent Page read access (as long as the locations

specified by the microprocessor fall within that Page) is equivalent to tPACC. Here again, CE selects the device

and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast

Page mode accesses are obtained by keeping A3 to A19 constant and changing A0 to A2 to select the specific

word, or changing A-1 to A2 to select the specific byte, within that page. See Figure 5.2 for timing specifications.

Standby Mode

The MBM29PL160TD/BD has a standby mode, a CMOS standby mode (CE input hel at VCC ±0.3 V.), when the

current consumed is less than 50 µA. During Embedded Algorithm operation, VCC Active current (ICC2) is required

even CE = “H”. The device can be read with standard access time (tCE) from standby modes.

In the standby mode, the outputs are in the high-impedance state, independent of the OE input. If the device

is deselected during erasure or programming, the device will draw active current until the operation is completed.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of

MBM29PL160TD/BD data. This mode can be used effectively with an application requesting low power

consumption such as handy terminals.

To activate this mode, MBM29PL160TD/BD automatically switches itself to low power mode when addresses

remain stable for 150 ns. It is not necessary to control CE, WE, and OE in this mode. During such mode, the

current consumed is typically 50 µA (CMOS Level).

Standard address access timings provide new data when addresses are changed. While in sleep mode, output

data is latched and always available to the system.

Output Disable

If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to

be in a high-impedance state.

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