MB91625 Series
- Harvard architecture allowing program access and data access to be executed simultaneously
- Instruction prefetch function has been added with 4 word instruction queue of CPU
• Instruction compatible with FR family CPU
- Additional bit search instructions
- No resource instructions and coprocessor instructions
• Maximum operating frequency
• CPU : 60 MHz
• Resources : 40 MHz
• DMA controller (DMAC)
• 8 channels
• Address space : 32 bits (4 Gbytes)
• Transfer modes : Block transfer/burst transfer/demand transfer
• Address update : Increment/decrement/fixed (increment/decrement step size of 1, 2, or 4)
• Transfer data length : Selectable from 8-bit, 16-bit, 32-bit
• Block size : 1 to 16
• Number of transfers : 1 to 65535
• Transfer requests
- Requests from software
- Interrupt requests from peripheral resources (interrupt requests are shared, including external interrupts)
• Reload functions : Reload can be specified on all channels
• Priority order : Fixed (ch.0 > ch.1 > ch.2 > ch.3 > ...) or round-robin
• Interrupt requests : Interrupts can be generated for transfer complete, transfer error, and transfer interrupted.
• Multifunction serial interface
• 4 channels with 16-byte FIFO, 8 channels without FIFO
• Operation mode is selectable from the followings for each channel (For ch.0, I2C is not available.)
• UART
- Full-duplex double buffer
- Selectable parity on/off
- Built-in dedicated baud rate generator
- External clock can be used as a serial clock
- Error detection function for parity, frame and overrun errors
• CSIO
- Full-duplex double buffer
- Built-in dedicated baud rate generator
- Overrun error detection function
• I2C
- Supports both standard mode (Max 100 kbps)and Fast mode (Max 400 kbps)
- Some channels are 5 V tolerant
• Interrupts
• Total of 32 external interrupts (some pins are 5 V tolerant)
• Interrupts from peripheral resources
• Programmable interrupt levels (16 levels)
• Can be used to return from stop mode, sleep mode
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DS07-16908-1E