MB88141A Просмотр технического описания (PDF) - Fujitsu

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MB88141A

D/A Converter for Digital Tuning (Compatible with I2C Bus)

Fujitsu 

MB88141A

(4) Channel Selection (8 bits)

C7 C6 C5 C4 C3 C2 C1 C0

× × × ×0 0 0 0

× × × ×0 0 0 1

Channel select

All channels selected *1

AO1 selected

× × × ×1 1 0 0

AO12 selected

× × × ×1 1 0 1

Don’t Care

× × × ×1 1 1 0

Don’t Care

× × × ×1 1 1 1

All channels selected *2

× : Don’t Care

*1: The 1 byte of data following the channel selection is set on all channels (all channels set to same data value) .

S Slave address (7 bits) 0 A

XXXX0000

A

D/A data (8 bits)

AP

*2: The 12 bytes of data following the channel selection are set on all channels (all channels set to separate data

values) .

S

Slave

address

0 A X X X X1 1 1 1 A

AO1 data

A

AO12 data A P

: Sent from master device

: Sent from MB88141A (slave device)

S : “Start” condition

P : “Stop” condition

A : “Acknowledge” output

Note: Setting will repeat, continuing in order from ch1, until the start and stop conditions are acknowledged.

(5) D/A Data (8 bits)

D7 D6 D5 D4 D3 D2 D1 D0

00000000

00000001

00000010

D/A output

≅ VSS

≅ (VREF / 256) × 1 + VSS

≅ (VREF / 256) × 2 + VSS

11111110

11111111

Note: VREF = VDD − VSS

≅ (VREF / 256) × 254 + VSS

≅ (VREF / 256) × 255 + VSS

9

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