MB86965 Просмотр технического описания (PDF) - Fujitsu

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MB86965

EtherCoupler™ ETHERNET CONTROLLER WITH 10BASE–T TRANSCEIVER

Fujitsu 

MB86965B

EtherCoupler™ ETHERNET CONTROLLER WITH 10BASE–T TRANSCEIVER

FACT SHEET

The MB86965B EtherCoupler™ Ethernet Controller is a

high–performance, highly integrated monolithic device, a

superset of the Fujitsu MB86965A, that incorporates a

network controller with buffer management, Manchester

encoder/decoder, 10BASE–T transceiver with on–chip

transmit and receive filters, and bus interface for a

PC/XT/AT/ISA bus. New features of the MB86965B not

present in its predecessor, the MB86965A, are summarized

below. The EtherCoupler allows implementation of adapter

solutions with as few as four chips. With its optional generic

bus mode, it is suitable for use directly on a microprocessor

bus, local bus or expansion bus.

A serial EEPROM can be interfaced to the chip for storage of

Ethernet ID and configuration settings. The EtherCoupler is

designed to be configured electronically, thus eliminating

the jumpers typically used to configure system network

adapters. When either the reset pin is activated, or a

‘software reset’ is issued by writing any value to any

on–chip address in the range x18 to x1F(hex), the

MB86965B will download three essential configuration

parameters from the EEPROM to BMPR19.

New Features of the MB86965B EtherCoupler

• Full–duplex capability

• External loopback mode allows testing of all 10BASE–T

interface circuits

• Write support for an external Flash boot PROM

• Software Reset now enables the system to fully reset and

re–initialize the controller without the need to activate the

system reset line

• 24 mA drive capability for IOCHRDY and IOS16 pins to

allow direct connection to the ISA bus

ADDITIONAL FEATURES

• Optional, generic host interface to connect to industry–

standard microprocessor busses

• Built–in interface for PC/XT™/AT® or compatible

busses

• Interface to serial EEPROM for Node ID and configura-

tion storage allows construction of jumperless, electroni-

cally–configurable adapters

• Automatic polarity correction on twisted–pair

10BASE–T receive twisted–pair cable

JANUARY 1994

• Allows automatic selection of non conflicting I/O address

for self–installing under software control

• High–performance, packet–buffer architecture pipelines

data for highest throughput

• On–chip buffer management controls buffer pointers to

reduce software overhead and improve performance

• Hash filter for multicast packet reception

• Manchester encoder/decoder tolerates input jitter up to

±18 ns

• Fully compliant with ISO/ANSI/IEEE 8802–3 specifica-

tions

• Two network ports, AUI and 10BASE–T, with automatic

port selection

• Integrated pulse shaper, and transmit and receive filters

• Selectable 150 Ω and 100 Ω termination for shielded or

unshielded twisted–pair cable, respectively

• Powerdown mode to reduce power dissipation in battery–

powered equipment

• Low–power CMOS technology

• Single 5–volt power supply

• 160–pin plastic quad flat package (PQFP)

160–Pin

Plastic Quad

Flat Pack

(PQFP)

TOP VIEW

Figure A. Pin Configuration

–1–

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