MB86960 Просмотр технического описания (PDF) - Fujitsu

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MB86960

NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

Fujitsu 

MB86960

Transmit Interrupt Enable Register

This register contains the bits which enable or mask the

status bits in DLCR0 from generating interrupts. Only

bits 7, 2 and 1 can generate interrupts. The other bits are

not used. See Table 6.

Table 6. DLCR2 — Transmit Interrupt Enable Register

BIT SYMBOL TYPE

DESCRIPTION

7

INT EN

R INTERRUPT ENABLE: When high, enables TX DONE to generate interrupt.

W See also DLCR0<7>.

0

6

0

N RESERVED: Write 0.

0

5

INT EN

N RESERVED: Write 0.

0

4

0

N RESERVED: Write 0.

0

3

0

N RESERVED: Write 0.

0

2

INT EN

R INTERRUPT ENABLE: When high, enables COL to generate interrupt.

W See also DLCR0<2>.

0

1

INT EN

R INTERRUPT ENABLE: When high, enables 16 COL to generate interrupt.

W See also DLCR0<1>.

0

0

0

N RESERVED: Write 0.

0

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