MB86065 Просмотр технического описания (PDF) - Fujitsu
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MB86065 Datasheet PDF : 2 Pages
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The Fujitsu MB86064 and MB86065
High-Performance Digital to Analog Converters
Control Interface
(1.8V LVCMOS)
RF Clock Input
(½ DAC rate)
Port A Data Input
(14-bit LVDS)
Loop-Clock Input
(LVDS)
Loop-Clock Output
(LVDS)
Port B Data Input
(14-bit LVDS)
4-wire Serial
Control Interface
Waveform
Memory
A
(16k Points)
Waveform
Memory
B
(16k Points)
÷
1, 2, 4, 8
÷
1, 2, 4, 8
Clock Output 1
(LVDS)
Clock Output 2
(LVDS)
Double-Edge
clocked
DAC A
(14-bit)
Analog Output A
DAC B
(14-bit)
(MB86064 only)
Analog Output B
Description
The MB86064 and MB86065 are part of the Fujitsu
second generation of high-performance digital to
analog converters (DACs).
• MB86064 Dual 14-bit 1.0GSa/s DAC
• MB86065 Single 14-bit 1.3GSa/s DAC
The MB86064 is ideally suited to radio applications,
providing dual transmit or transmit with diversity. The
MB86065 supports conversion rates up of up to
1.3GSa/s, which enables higher generating frequencies
combined with wider spurious-free generating regions.
Both devices feature the market’s shortest propagation
delay combined with superior time-domain response for
control-based applications that require low latency.
Robust data interfacing to compatible FPGAs and
ASICs is assured by a proprietary Loop-Clock
architecture. This unique solution automatically
maintains critical clock-to-data timing across variations
in process, voltage and temperature (PVT). No
calibration is required during production or lifetime
operation, reducing total system costs.
Features
• Delivers higher frequency, direct-IF generation
compared to competitors’alternatives
• Avoids the analog and digital overhead of IQ and
direct conversion architectures
• Supports multiple, including non-contiguous,
narrow and wide-band signal generation
• Integrated waveform memory for storing test and
evaluation vectors on-chip
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