MAX9320B Просмотр технического описания (PDF) - Maxim Integrated

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производитель

MAX9320B

1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver

Maxim Integrated 

1:2 Differential PECL/ECL/LVPECL/LVECL

Clock and Data Driver

Typical Operating Characteristics (continued)

(VCC = 5V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with

50Ω to VCC - 2V, TA = +25°C, unless otherwise noted.)

PROPAGATION DELAY vs. HIGH VOLTAGE

OF DIFFERENTIAL INPUT, VIHD

220

VIHD - VILD = 0.5V

215

tPLHD

210

205

200

195

tPHLD

190

1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6

VIHD (V)

PROPAGATION DELAY vs. TEMPERATURE

240

230

tPLHD

220

210

200

190

tPHLD

180

170

160

-40 -15

10

35

60

85

TEMPERATURE (°C)

Pin Description

PIN

NAME

FUNCTION

1

Q0

Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.

2

Q0

Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.

3

Q1

Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.

4

Q1

Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.

5

VEE

Negative Supply Voltage

6

D

Inverting Differential Input. 50kΩ pullup to VCC and 100kΩ pulldown to VEE.

7

D

Noninverting Differential Input. 80kΩ pullup to VCC and 60kΩ pulldown to VEE.

8

VCC

Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the

capacitors as close to the device as possible with the smaller value capacitor closest to the device.

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