MAX9320AEKA(2001) Просмотр технического описания (PDF) - Maxim Integrated
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MAX9320AEKA Datasheet PDF : 9 Pages
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1:2 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
D
VIHD
VIHD -VILD
D
VILD
tPLHD
Q_
Q
tPHLD
VOH
VOH -VOL
VOL
(Q_) - (Q_)
80%
80%
0 (DIFFERENTIAL)
0 (DIFFERENTIAL)
20%
20%
tR
tF
Figure 1. Differential Transition Time and Propagation Delay
Timing Diagram
Detailed Description
The MAX9320/MAX9320A low-skew, 1-to-2 differential
drivers are designed for clock and data distribution. For
interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock and data distri-
bution in systems with a nominal +2.5V or +3.3V sup-
ply. For differential LVECL operation, these devices
operate from a -2.25V to -3.8V supply.
Inputs
The maximum magnitude of the differential input from D
to D is VCC - VEE or 3.0V, whichever is less. This limit
also applies to the difference between any reference
voltage input and a single-ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting input, D, is biased with a 60kΩ pullup to
VCC and a 100kΩ pulldown to VEE. The noninverting
input, D, is biased with a 100kΩ pulldown to VEE.
Specifications for the high and low voltages of the dif-
ferential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously (VILD cannot
be higher than VIHD).
Outputs
Output levels are referenced to VCC and are consid-
ered LVPECL or LVECL, depending on the level of the
VCC supply. With VCC connected to a positive supply
and VEE connected to GND, the outputs are LVPECL.
The outputs are LVECL when VCC is connected to GND
and VEE is connected to a negative supply.
A single-ended input of ±100mV around a reference
voltage or a differential input of at least ±100mV switch-
es the outputs to the VOH and VOL levels specified in
the DC Electrical Characteristics table.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF value
capacitor closest to the device. Use multiple parallel
vias for low inductance.
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9320/MAX9320A. Connect each
signal of a differential input or output to a 50Ω charac-
teristic impedance trace. Minimize the number of vias
to prevent impedance discontinuities. Reduce reflec-
tions by maintaining the 50Ω characteristic impedance
through connectors and across cables. Reduce skew
within a differential pair by matching the electrical
length of the traces.
The exposed-pad (EP) SO package can be soldered to
the PC board for enhanced thermal performance. If the
EP is not soldered to the PC board, the thermal resis-
tance is the same as the regular SO package. The EP
is connected to the chip VEE supply. Be sure that the
pad does not touch signal lines or other supplies.
Contact the Maxim Packaging department for guide-
lines on the use of EP packages.
Output Termination
Terminate outputs through 50Ω to VCC - 2V or use an
equivalent Thevenin termination. Terminate both out-
puts and use the same termination on each for the low-
est output-to-output skew. When a single-ended signal
is taken from a differential output, terminate both out-
puts. For example, if Q0 is used as a single-ended out-
put, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 182
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