Quad LVDS Line Driver with High-ESD
Tolerance and Flow-Through Pinout
2V TO VCC + 1
-1V TO 0.8V
IN_
VOD
Figure 1. Driver VOD and VOS Test Circuit
OUT_+
RL / 2
VOS
RL / 2
OUT_-
Test Circuits/Timing Diagrams
CL
PULSE
GENERATOR
IN_
50Ω
OUT_ +
RL
OUT_ -
CL
Figure 2. Transition Time and Propagation Delay Test Circuit
IN_
OUT_-
OUT_+
0.5 x VCC
tPLHD
0 (DIFFERENTIAL)
0.5 x VCC
tPHLD
VCC + 1V
VCC
0
-1V
0 (DIFFERENTIAL)
80%
80%
0 (DIFFERENTIAL)
0 (DIFFERENTIAL)
VDIFF
20%
VDIFF = (OUT_+) - (OUT_-)
20%
tR
tF
Figure 3. Transition Time and Propagation Delay Waveform Timing
2V TO VCC + 1V
-1V TO 0.8V
IN_
PULSE
GENERATOR
EN
EN
50Ω
CL
OUT_+
RL / 2
RL / 2
+1.2V
OUT_-
CL
1/4 MAX9178
Figure 4. High-Impedance Delay Test Circuit
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