MAX9000 Просмотр технического описания (PDF) - Altera Corporation

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MAX9000

Programmable Logic Device Family

Altera Corporation 

MAX 9000 Programmable Logic Device Family Data Sheet

...and More

Features

■ Programmable macrocell flipflops with individual clear, preset,

clock, and clock enable controls

■ Programmable security bit for protection of proprietary designs

■ Software design support and automatic place-and-route provided by

Altera’s MAX+PLUS® II development system on Windows-based

PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM

RISC System/6000 workstations

■ Additional design entry and simulation support provided by EDIF

2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),

Verilog HDL, VHDL, and other interfaces to popular EDA tools from

manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,

OrCAD, Synopsys, Synplicity, and VeriBest

■ Programming support with Altera’s Master Programming Unit

(MPU), BitBlasterTM serial download cable, ByteBlasterTM parallel

port download cable, and ByteBlasterMVTM parallel port download

cable, as well as programming hardware from third-party

manufacturers

■ Offered in a variety of package options with 84 to 356 pins (see

Table 2)

Table 2. MAX 9000 Package Options & I/O Counts Note (1)

Device

EPM9320

EPM9320A

EPM9400

EPM9480

EPM9560

EPM9560A

84-Pin

PLCC

60 (2)

60 (2)

59 (2)

–

–

–

208-Pin

RQFP

132

132

139

146

153

153

240-Pin

RQFP

–

–

159

175

191

191

280-Pin

PGA

168

–

–

–

216

–

304-Pin

RQFP

–

–

–

–

216

–

356-Pin

BGA

168

168

–

–

216

216

Notes:

(1) MAX 9000 device package types include plastic J-lead chip carrier (PLCC), power

quad flat pack (RQFP), ceramic pin-grid array (PGA), and ball-grid array (BGA)

packages.

(2) Perform a complete thermal analysis before committing a design to this device

package. See Application Note 74 (Evaluating Power for Altera Devices).

2

Altera Corporation

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